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? 2016 microchip technology inc. ds00002117c-page 1 features ? single-chip 10/100/1000 mbps ethernet trans- ceiver suitable for i eee 802.3 ap plications ? rgmii timing supports on-chip delay according to rgmii version 2.0, with programming options for external delay and making adjustments and corrections to tx and rx timing paths ? rgmii with 3.3v/2.5v/1.8v tolerant i/os ? auto-negotiation to automatically select the highest link-up speed (10/100/1000 mbps) and duplex (half/full) ? on-chip termination resistors for the differential pairs ? on-chip ldo controller to support single 3.3v supply operation ? requires only one external fet to generate 1.2v for the core ? jumbo frame support up to 16 kb ? 125 mhz reference clock output ? energy detect power-down mode for reduced power consumption when the cable is not attached ? wake-on-lan (wol) support with robust cus- tom-packet detection ? aec-q100 qualified for automotive applications (KSZ9031RNXua, KSZ9031RNXva) ? programmable led outputs for link, activity, and speed ? baseline wander correction ? linkmd tdr-based cable diagnostic to identify faulty copper cabling ? parametric nand tree support to detect faults between chip i/os and board ? loopback modes for diagnostics ? automatic mdi/mdi-x crossover to detect and correct pair swap at all speeds of operation ? automatic detection and correction of pair swaps, pair skew, and pair polarity ? mdc/mdio management interface for phy reg- ister configuration ? interrupt pin option ? power-down and power-saving modes ? operating voltages - core (dvddl, avddl, avddl_pll): 1.2v (external fet or regulator) - vdd i/o (dvddh): 3.3v, 2.5v, or 1.8v - transceiver (avddh): 3.3v or 2.5v (com- mercial temp.) ? 48-pin qfn (7 mm 7 mm) package target applications ? laser/network printer ? network attached storage (nas) ? network server ? gigabit lan on motherboard (glom) ? broadband gateway ? gigabit soho/smb router ?iptv ? ip set-top box ? game console ? triple-play (data, voice, video) media center ? media converter KSZ9031RNX gigabit ethernet transceiver with rgmii support
KSZ9031RNX ds00002117c-page 2 ? 2016 microchip technology inc. to our valued customers it is our intention to provide our valued customers with the bes t documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regarding this publication, please contact the marketing co mmunications department via e-mail at docerrors@microchip.com . we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data s heet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the versi on number, (e.g., ds30000000a is version a of document ds30000000). errata an errata sheet, describing minor operati onal differences from the data sheet and recommended workarounds, may exist for cur- rent devices. as device/doc umentation issues become known to us, we will publish an errata s heet. the errata will specify the revision of silicon and revision of document to which it applies. to determine if an errata sheet exis ts for a particular device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please spec ify which device, revision of silicon and data sheet (include -literature number) yo u are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products.
? 2016 microchip technology inc. ds00002117c-page 3 KSZ9031RNX table of contents 1.0 introduction .............................................................................................................. ....................................................................... 4 2.0 pin description and configuration ......................................................................................... ......................................................... 5 3.0 functional description .................................................................................................... .............................................................. 13 4.0 register descriptions ..................................................................................................... ............................................................... 31 5.0 operational charac teristics ............................................................................................... ............................................................ 52 6.0 electrical characteristics ................................................................................................ ............................................................... 53 7.0 timing diagrams ........................................................................................................... ................................................................ 57 8.0 reset circuit ............................................................................................................. .................................................................... 63 9.0 reference circuits ? le d strap-in pins .................................................................................... .................................................. 65 10.0 reference clock - connection and selection ............................................................................... .............................................. 66 11.0 on-chip ldo controller - mosfet selection ................................................................................ ............................................ 66 12.0 magnetic - connection and selection ...................................................................................... ................................................... 67 13.0 package outlines ......................................................................................................... ............................................................... 69 appendix a: data sheet revision history ....................................................................................... .................................................... 74 the microchip web site ........................................................................................................ .............................................................. 75 customer change notification service .......................................................................................... ..................................................... 75 customer support .............................................................................................................. ................................................................. 75 product identification system ................................................................................................. ............................................................ 76
KSZ9031RNX ds00002117c-page 4 ? 2016 microchip technology inc. 1.0 introduction 1.1 general description the KSZ9031RNX is a completely integrated triple-s peed (10base-t/100base-tx/1000base-t) ethernet physical- layer transceiver for transmission and reception of data on standard cat-5 unshielded twisted pair (utp) cable. the KSZ9031RNX provides the reduced gigabit media independe nt interface (rgmii) for di rect connection to rgmii macs in gigabit ethernet processors and s witches for data transfer at 10/100/1000 mbps. the KSZ9031RNX reduces board cost and simplifies board la yout by using on-chip termination resistors for the four differential pairs and by integrating an ldo controller to drive a low-cost mosfet to supply the 1.2v core. the KSZ9031RNX offers diagnostic features to facilitate system bring-up and debugging in production testing and in product deployment. parametric nand tr ee support enables fault detection betw een ksz9031 i/os and the board. the linkmd ? tdr-based cable diagnostic identifies faulty copper cabling. remote and local loopback functions verify ana- log and digital data paths. the standard KSZ9031RNX is available in a 48-pin, lead-free qfn package, and the aec-q100 automotive qualified parts, KSZ9031RNXua and KSZ9031RNXva, are available in a 48-pin lead-free wqfn package. figure 1-1: system block diagram rgmii 10/100/1000mbps rgmii ethernet mac mdc/mdio management KSZ9031RNX ldo controller on-chip termination resistors vin 3.3va vout 1.2v (for core voltages) magnetics rj-45 connector media types 10base-t 100base-tx 1000base-t (system power circuit) pme_n
? 2016 microchip technology inc. ds00002117c-page 5 KSZ9031RNX 2.0 pin description and configuration figure 2-1: 48-qfn pin assignment (top view) 1 txrxp_a led2/ phyad1 41 42 43 44 45 46 47 48 paddle ground (on bottom of chip) 37 38 39 40 2 txrxm_a 3 4 5 avddl 6 avddh 7 8 9 10 txrxp_b 11 txrxm_b avddl 20 19 18 17 16 15 14 13 24 23 22 21 led1 / pme_n1 / phyad0 dv dd h txd0 dvddl txd2 txd3 dvddl 36 35 34 33 32 31 30 29 28 27 26 25 dvddl tx_en rxd1/ mode1 rxd0/ mode0 rx_dv/ clk125_en dvddh vss rx_clk/ phyad2 reset_n iset nc xi xo avddl_pll ldo_o dvddh clk125_ndo/ led_mode dvddl int_n/ pme_n2 mdio txd1 dvddl KSZ9031RNX 12 avddh txrxp_c txrxm_c txrxp_d txrxm_d mdc rxd2/ mode2 rxd3/ mode3 dvddl gtx_clk nc
KSZ9031RNX ds00002117c-page 6 ? 2016 microchip technology inc. table 2-1: signals - KSZ9031RNX pin number pin name type note 2-1 description 1 avddh p 3.3v/2.5v (commercial temp only) analog v dd 2 txrxp_a i/o media dependent interface[0], positive signal of differential pair 1000base-t mode: txrxp_a corresponds to bi_da+ for mdi configuration and bi_db+ for mdi- x configuration, respectively. 10base-t/100base-tx mode: txrxp_a is the positive transmit signal (tx+) for mdi configuration and the positive receive signal (rx+) for mdi-x configuration, respectively. 3 txrxm_a i/o media dependent interface[0], negat ive signal of differential pair 1000base-t mode: txrxm_a corresponds to bi_da? for mdi configuration and bi_db? for mdi-x configuration, respectively. 10base-t/100base-tx mode: txrxm_a is the negative transmit signal (tx?) for mdi configuration and the negative receive signal (rx?) for mdi-x configuration, respectively. 4 avddl p 1.2v analog v dd 5 txrxp_b i/o media dependent interface[1], positive signal of differential pair 1000base-t mode: txrxp_b corresponds to bi_db+ for mdi configuration and bi_da+ for mdi- x configuration, respectively. 10base-t/100base-tx mode: txrxp_b is the positive receive signal (rx+) for mdi configuration and the positive transmit signal (tx+) for mdi-x configuration, respectively. 6 txrxm_b i/o media dependent interface[1], negat ive signal of differential pair 1000base-t mode: txrxm_b corresponds to bi_db? for mdi configuration and bi_da? for mdi-x configuration, respectively. 10base-t/100base-tx mode: txrxm_b is the negative receive signal (rx?) for mdi configuration and the negative transmit signal (tx?) for mdi-x configuration, respectively. 7 txrxp_c i/o media dependent interface[2], positive signal of differential pair 1000base-t mode: txrxp_c corresponds to bi_dc+ for mdi configuration and bi_dd+ for mdi-x configuration, respectively. 10base-t/100base-tx mode: txrxp_c is not used. 8 txrxm_c i/o media dependent interface[2], negat ive signal of differential pair 1000base-t mode: txrxm_c corresponds to bi_dc? for mdi configuration and bi_dd? for mdi-x configuration, respectively. 10base-t/100base-tx mode: txrxm_c is not used. 9 avddl p 1.2v analog v dd
? 2016 microchip technology inc. ds00002117c-page 7 KSZ9031RNX 10 txrxp_d i/o media dependent interface[3], positive signal of differential pair 1000base-t mode: txrxp_d corresponds to bi_dd+ for mdi configuration and bi_dc+ for mdi-x configuration, respectively. 10base-t/100base-tx mode: txrxp_d is not used. 11 txrxm_d i/o media dependent interface[3], negat ive signal of differential pair 1000base-t mode: txrxm_d corresponds to bi_dd? for mdi configuration and bi_dc? for mdi-x configuration, respectively. 10base-t/100base-tx mode: txrxm_d is not used. 12 avddh p 3.3v/2.5v (commercial temp only) analog v dd 13 nc ? no connect. this pin is not bonded and can be connected to digital ground for footprint compatibility with the ksz9021rn gigabit phy. 14 dvddl p 1.2v digital v dd table 2-1: signals - KSZ9031RNX (continued) pin number pin name type note 2-1 description
KSZ9031RNX ds00002117c-page 8 ? 2016 microchip technology inc. 15 led2/ phyad1 i/o led output: programmable led2 output config mode: the pull-up/pull-down val ue is latched as phyad[1] during power-up/reset. see the strap-in options - KSZ9031RNX section for details. the led2 pin is programmed by the led_mode strapping option (pin 41), and is defined as follows: single-led mode link pin state led definition link off h off link on (any speed) l on tri-color dual-led mode link/activity pin state led definition led2 led1 led2 led1 link off h h off off 1000 link/no activity l h on off 1000 link/activity (rx, tx) toggle h blinking off 100 link/no activity h l off on 100 link/activity (rx, tx) h toggle off blinking 10 link/no activity l l on on 10 link/activity (rx, tx) toggle toggle blinking blinking for tri-color dual-led mode, led2 works in conjunction with led1 (pin 17) to indicate 10 mbps link and activity. 16 dvddh p 3.3v, 2.5v, or 1.8v digital v dd_i/o table 2-1: signals - KSZ9031RNX (continued) pin number pin name type note 2-1 description
? 2016 microchip technology inc. ds00002117c-page 9 KSZ9031RNX 17 led1/ phyad0/ pme_n1 i/o led1 output: programmable led1 output config mode: the voltage on this pin is sampled and latched during the power-up/reset process to determi ne the value of phyad[0]. see the strap-in options - KSZ9031RNX section for details. pme_n output: programmable pme_n output (pin option 1). this pin function requires an external pull-up resistor to dvddh (digital v dd_i/o ) in a range from 1.0 k ? to 4.7 k ? . when asserted low, this pin signals that a wol event has occurred. this pin is not an open-drain for all operating modes. the led1 pin is programmed by the led_mode strapping option (pin 41), and is defined as follows: single-led mode activity pin stat e led definition no activity h off activity (rx, tx) toggle blinking tri-color dual-led mode link/activity pin state led definition led2 led1 led2 led1 link off h h off off 1000 link/no activity l h on off 1000 link/activity (rx, tx) toggle h blinking off 100 link/no activity h l off on 100 link/activity (rx, tx) h toggle off blinking 10 link/no activity l l on on 10 link/activity (rx, tx) toggle toggle blinking blinking for tri-color dual-led mode, led1 works in conjunction with led2 (pin 15) to indicate 10 mbps link and activity. 18 dvddl p 1.2v digital v dd 19 txd0 i rgmii mode: rgmii td0 (transmit data 0) input 20 txd1 i rgmii mode: rgmii td1 (transmit data 1) input 21 txd2 i rgmii mode: rgmii td2 (transmit data 2) input 22 txd3 i rgmii mode: rgmii td3 (transmit data 3) input 23 dvddl p 1.2v digital v dd 24 gtx_clk i rgmii mode: rgmii txc (transmit reference clock) input table 2-1: signals - KSZ9031RNX (continued) pin number pin name type note 2-1 description
KSZ9031RNX ds00002117c-page 10 ? 2016 microchip technology inc. 25 tx_en i rgmii mode: rgmii tx_ctl (transmit control) input 26 dvddl p 1.2v digital v dd 27 rxd3/ mode3 i/o rgmii mode: rgmii rd3 (receive data 3) output config mode: the pull-up/pull-down va lue is latched as mode3 during power-up/reset. see the strap-in options - KSZ9031RNX section for details. 28 rxd2/ mode2 i/o rgmii mode: rgmii rd2 (receive data 2) output config mode: the pull-up/pull-down va lue is latched as mode2 during power-up/reset. see the strap-in options - KSZ9031RNX section for details. 29 vss gnd digital ground 30 dvddl p 1.2v digital v dd 31 rxd1/ mode1 i/o rgmii mode: rgmii rd1 (receive data 1) output config mode: the pull-up/pull-down va lue is latched as mode1 during power-up/reset. see the strap-in options - KSZ9031RNX section for details. 32 rxd0/ mode0 i/o rgmii mode: rgmii rd0 (receive data 0) output config mode: the pull-up/pull-down va lue is latched as mode0 during power-up/reset. see the strap-in options - KSZ9031RNX section for details. 33 rx_dv/ clk125_en i/o rgmii mode: rgmii rx_ctl (receive control) output config mode: latched as clk125_ ndo output enable during power-up/ reset. see the strap-in options - KSZ9031RNX section for details. 34 dvddh p 3.3v, 2.5v, or 1.8v digital v dd_i/o 35 rx_clk/ phyad2 i/o rgmii mode: rgmii rxc (receive reference clock) output config mode: the pull-up/pull-down val ue is latched as phyad[2] during power-up/reset. see the strap-in options - KSZ9031RNX section for details. 36 mdc ipu management data clock input this pin is the input reference clock for mdio (pin 37). 37 mdio ipu/o management data input/output this pin is synchronous to mdc (pin 36) and requires an external pull-up resistor to dvddh (digital v dd_i/o ) in a range from 1.0 k ? to 4.7 k ? . 38 int_n/ pme_n2 o interrupt output: programmable interrupt output, with register 1bh as the interrupt control/status register, for programming the interrupt conditions and reading the interrupt status. register 1fh, bit [14] sets the interrupt output to active low (default) or active high. pme_n output: programmable pme_n ou tput (pin option 2). when asserted low, this pin signals that a wol event has occurred. for interrupt (when active low) and pme functions, this pin requires an exter- nal pull-up resistor to dvddh (digital v dd_i/o ) in a range from 1.0 k ? to 4.7 k ? . this pin is not an open-drain for all operating modes. 39 dvddl p 1.2v digital v dd 40 dvddh p 3.3v, 2.5v, or 1.8v digital v dd_i/o table 2-1: signals - KSZ9031RNX (continued) pin number pin name type note 2-1 description
? 2016 microchip technology inc. ds00002117c-page 11 KSZ9031RNX note 2-1 p = power supply gnd = ground i = input o = output i/o = bi-directional ipu = input with internal pull-up (see section 6.0, "electri cal characteristics" for value). ipu/o = input with in ternal pull-up (see section 6.0, "electrical characteristics" for value) during power-up/reset; out put pin otherwise. 41 clk125_ndo/ led_mode i/o 125 mhz clock output this pin provides a 125 mhz reference clock output option for use by the mac. config mode: the pull-up/pull-down val ue is latched as led_mode during power-up/reset. see the strap-in options - KSZ9031RNX section for details. 42 reset_n ipu chip reset (active low) hardware pin configurations are strapped-in at the de-assertion (rising edge) of reset_n. see the strap-in options - KSZ9031RNX section for details. 43 ldo_o o on-chip 1.2v ldo controller output this pin drives the input gate of a p-channel mosfet to generate 1.2v for the chip?s core voltages. if the system provides 1.2v and this pin is not used, it can be left floating. 44 avddl_pll p 1.2v analog v dd for pll 45 xo o 25 mhz crystal feedback this pin is a no connect if an oscillat or or external clock source is used. 46 xi i crystal/oscillator/external clock input 25 mhz 50 ppm tolerance 47 nc ? no connect this pin is not bonded and can be connected to avddh power for footprint compatibility with the ksz9021rn gigabit phy. 48 iset i/o set the transmit output level connect a 12.1 k ? 1% resistor to ground on this pin. paddle p_gnd gnd exposed paddle on bottom of chip connect p_gnd to ground. table 2-1: signals - KSZ9031RNX (continued) pin number pin name type note 2-1 description
KSZ9031RNX ds00002117c-page 12 ? 2016 microchip technology inc. pin strap-ins are latched durin g power-up or reset. in some systems, the mac receive input pins may be driven during power-up or reset, and consequently caus e the phy strap-in pins on the rgmii signals to be latched to an incorrect configuration. in this case, external pul l-up or pull-down resistors should be added on the phy strap-in pins to ensure the phy is configured to the correct pin strap-in mode. note 2-2 i/o = bi-directional. table 2-2: strap-in options - KSZ9031RNX pin number pin name type note 2-2 description 35 15 17 phyad2 phyad1 phyad0 i/o i/o i/o the phy address, phyad[2:0], is sampled and latched at power-up/ reset and is configurable to any value from 0 to 7. each phy address bit is configured as follows: pull-up = 1 pull-down = 0 phy address bits [4:3] are always set to ?00?. 27 28 31 32 mode3 mode2 mode1 mode0 i/o i/o i/o i/o the mode[3:0] strap-in pins are sampled and latched at power-up/ reset and are defined as follows: mode[3:0] mode 0000 reserved - not used 0001 reserved - not used 0010 reserved - not used 0011 reserved - not used 0100 nand tree mode 0101 reserved - not used 0110 reserved - not used 0111 chip power-down mode 1000 reserved - not used 1001 reserved - not used 1010 reserved - not used 1011 reserved - not used 1100 rgmii mode - advertise 1000base-t full-duplex only 1101 rgmii mode - advertise 1000base-t full- and half- duplex only 1110 rgmii mode - advertise all capabilities (10/100/1000 speed half-/full-duplex), except 1000base-t half- duplex 1111 rgmii mode - advertise all capabilities (10/100/1000 speed half-/full-duplex) 33 clk125_en i/o clk125_en is sampled and latched at power-up/reset and is defined as follows: pull-up (1) = enable 125 mhz clock output pull-down (0) = disable 125 mhz clock output pin 41 (clk125_ndo) provides the 125 mhz reference clock output option for use by the mac. 41 led_mode i/o led_mode is sampled and latched at power-up/reset and is defined as follows: pull-up (1) = single-led mode pull-down (0) = tri-color dual-led mode
? 2016 microchip technology inc. ds00002117c-page 13 KSZ9031RNX 3.0 functional description the KSZ9031RNX is a completely integrated triple -speed (10base-t/100base-tx/1000 base-t) ethernet physical layer transceiver solution for transmission and reception of data over a standard cat-5 unshielded twisted pair (utp) cable. the KSZ9031RNX reduces board cost and simplifies board la yout by using on-chip termination resistors for the four differential pairs and by integrating an ldo controller to drive a low-cost mosfet to supply the 1.2v core. on the copper media interface, the KSZ9031RNX can automati cally detect and correct for differential pair misplace- ments and polarity reversals, and correct propagation delays and re-sync timing between the four differential pairs, as specified in the ieee 802.3 standard for 1000base-t operation. the KSZ9031RNX provides the rgmii interface for connection to rgmii macs in gigabit ethernet processors and switches for data transfer at 10/100/1000 mbps. figure 3-1 shows a high-level block diagram of the KSZ9031RNX. figure 3-1: KSZ9031RNX block diagram 3.1 10base-t/100base-tx transceiver 3.1.1 100base-tx transmit the 100base-tx transmit function perfo rms parallel-to-serial conversion, 4b/5 b coding, scrambling, nrz-to-nrzi con- version, and mlt-3 encoding and transmission. the circuitry starts with a parallel-to-serial conversion, whic h converts the mii data from the mac into a 125 mhz serial bit stream. the data and control stream is then converted into 4b/5b coding, followed by a scrambler. the serialized data is further converted from nrz-to-nrzi format, and then transmitted in mlt-3 current output. the output current is set by an external 12.1 k ? 1% resistor for the 1:1 transformer ratio. the output signal has a typical rise/fall time of 4 ns and complies with the ansi tp-pmd standard regarding amplitude balance, and overshoot. the wa ve-shaped 10base-t outpu t is also incorpor ated into the 100 base-tx transmitter. 3.1.2 100base-tx receive the 100base-tx receiver function perfo rms adaptive equalization, dc restorati on, mlt-3-to-nrzi conversion, data and clock recovery, nrzi-to-nrz conversion, de-scrambli ng, 4b/5b decoding, and serial-to-parallel conversion. the receiving side starts with the equalization filter to com pensate for inter-symbol interfer ence (isi) over the twisted pair cable. because the amplitude loss and phase distortion ar e a function of the cable lengt h, the equalizer must adjust its characteristics to optimize performanc e. in this design, the variable equaliz er makes an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, then t unes itself for optimization. this is an ongoing process and self-adjusts against environmental changes such as temperature variations. media interface pma tx10/100/1000 pma rx1000 pma rx100 pma rx10 clock reset pcs10 auto- negotiation pcs100 pcs1000 interface led drivers configurations rgmii
KSZ9031RNX ds00002117c-page 14 ? 2016 microchip technology inc. next, the equalized signal goes through a dc-restoration and data-conversion block. the dc-restoration circuit com- pensates for the effect of baseline wander and improves the dynamic range. the differential data conversion circuit con- verts the mlt-3 format back to nrzi. th e slicing threshold is also adaptive. the clock-recovery circuit extracts the 125 mhz clock from the edges of the nrzi signal. this recovered clock is then used to convert the nrzi signal into the nrz format. this si gnal is sent through the de-scrambler followed by the 4b/ 5b decoder. finally, the nrz serial data is converted to th e rgmii format and provided as the input data to the mac. 3.1.3 scrambler/de-scrambler (100base-tx only) the purpose of the scrambler is to spr ead the power spectrum of the signal to reduce electromagnetic interference (emi) and baseline wander. transmitted data is scrambled using an 11-bit wide linear feedback shift register (lfsr). the scrambler generates a 2047-bit non-repetitive sequence, then the receiver de-scrambles the incoming data stream using the same sequence as at the transmitter. 3.1.4 10base-t transmit the 10base-t output drivers are incorpor ated into the 100base-tx drivers to allow for transmission with the same magnetic. the drivers perform internal wave-shaping and pre-emphasis, and output sig nals with typical amplitude of 2.5v peak for standard 10base-t mode and 1.75v peak for energy-efficient 10base-te mode. the 10base-t/ 10base-te signals have harmonic contents that are at least 31 db be low the fundamental fr equency when driven by an all-ones manchester-encoded signal. 3.1.5 10base-t receive on the receive side, input buffer and level-detecting squelch circuits are used. a differential input receiver circuit and a phase-locked loop (pll) perform the decoding function. the manchester-encoded data stream is separated into clock signal and nrz data. a squelch circuit rejects signals with levels less than 300 mv or with short pulse widths to prevent noises at the receive inputs from falsely triggering the dec oder. when the input exceeds th e squelch limit, the pll locks onto the incoming signal and the KSZ9031RNX decodes a data fr ame. the receiver clock is maintained active during idle periods between receiving data frames. the KSZ9031RNX removes all 7 bytes of the preamble and pres ents the received frame starting with the sfd (start of frame delimiter) to the mac. auto-polarity correction is provided for the receiving differenti al pair to automatically swap and fix the incorrect +/? polar- ity wiring in the cabling. 3.2 1000base-t transceiver the 1000base-t transceiver is based-on a mixed-signa l/digital-signal processing (dsp) architecture, which includes the analog front-end, digital channel equalizers, trellis enc oders/decoders, echo c ancelers, cross-talk cancelers, preci- sion clock recovery scheme, and power-efficient line drivers. figure 3-2 shows a high-level block diagram of a single channel of the 1000base-t transceiver for one of the four dif- ferential pairs.
? 2016 microchip technology inc. ds00002117c-page 15 KSZ9031RNX figure 3-2: KSZ9031RNX 1000base- t block diagram - single channel 3.2.1 analog echo-cancellation circuit in 1000base-t mode, the analog echo-cancellation circuit helps to reduce the near-end echo. this analog hybrid circuit relieves the burden of the adc and the adaptive equalizer. this circuit is disabled in 10base-t/100base-tx mode. 3.2.2 automatic gain control (agc) in 1000base-t mode, the automati c gain control (agc) circuit provides initia l gain adjustment to boost up the signal level. this pre-conditioning circuit is used to impr ove the signal-to-noise ratio of the receive signal. 3.2.3 analog-to-digital converter (adc) in 1000base-t mode, the analog-t o-digital converter (adc) di gitizes the incoming signal. adc performance is essen- tial to the overall performance of the transceiver. this circuit is disabled in 10base-t/100base-tx mode. 3.2.4 timing recovery circuit in 1000base-t mode, the mixed-signal clock recovery circ uit together with the digital phase-locked loop is used to recover and track the incoming timing information from the received data. the digital phase-locked loop has very low long-term jitter to maximize the signal-to-noise ratio of the receive signal. the 1000base-t slave phy must transmit the exact receiv e clock frequency recovered from the received data back to the 1000base-t master phy. otherwise, the master and slav e will not be synchronized after long transmission. this also helps to facilitate echo cancellation and next removal. 3.2.5 adaptive equalizer in 1000base-t mode, the ad aptive equalizer provides the following functions: ? detection for partial response signaling ? removal of next and echo noise ? channel equalization signal quality is degraded by residual echo that is not re moved by the analog hybrid because of impedance mismatch. the KSZ9031RNX uses a digital echo canceler to fu rther reduce echo components on the receive signal. in 1000base-t mode, data transmission and reception occurs si multaneously on all four pairs of wires (four channels). this results in high-frequency cross-talk coming from adjacent wires. the KSZ9031RNX uses three next cancelers on each receive channel to minimize the cross- talk induced by the other three channels. clock generation baseline wander compensation echo canceller transmit block next canceller next canceller next canceller rx- adc agc + ffe slicer clock and phase recovery auto - negotiation pma state machines mii registers mii management control dfe analog hybrid pcs state machines pair swap and align unit descrambler + decoder side -stream scrambler and symbol encoder led driver xtal other channels tx signal rx signal
KSZ9031RNX ds00002117c-page 16 ? 2016 microchip technology inc. in 10base-t/100base-tx mode, the adaptive equalizer needs only to remove the inter-symbol interference and recover the channel loss from the incoming data. 3.2.6 trellis encoder and decoder in 1000base-t mode, the transmitted 8-bit data is scrambled into 9- bit symbols and further encoded into 4d-pam5 symbols. the initial scrambler seed is determined by th e specific phy address to reduce emi when more than one KSZ9031RNX is used on the same board. on the receiving si de, the idle stream is examined first. the scrambler seed, pair skew, pair order, and polarity must be resolved th rough the logic. the incoming 4d-pam5 data is then converted into 9-bit symbols and de-scrambled into 8-bit data. 3.3 auto mdi/mdi-x the automatic mdi/mdi-x feature eliminates the need to determ ine whether to use a straight cable or a crossover cable between the KSZ9031RNX and its link partner. this auto-sens e function detects the mdi/mdi-x pair mapping from the link partner, and assigns the mdi/mdi-x pair mapping of the KSZ9031RNX accordingly. table 3-1 shows the KSZ9031RNX 10/100/1000 pin config uration assignments for mdi/mdi-x pin mapping. auto mdi/mdi-x is enabled by default. it is disabled by wr iting a one to register 1ch, bit [6]. mdi and mdi-x mode is set by register 1ch, bit [7] if auto mdi/mdi-x is disabled. an isolation transformer with symmetrical transmit and rece ive data paths is recommended to support auto mdi/mdi-x. 3.4 pair-swap, alignment, and polarity check in 1000base-t mo de, the KSZ9031RNX ? detects incorrect channel order and automatically restores the pair order for the a, b, c, d pairs (four channels). ? supports 50 ns 10 ns difference in propagation delay between pairs of channels in accordance with the ieee 802.3 standard, and automatically corrects the data skew so the corrected four pairs of data symbols are synchro- nized. incorrect pair polarities of the differential si gnals are automatically corrected for all speeds. 3.5 wave shaping, slew-rate control, and partial response in communication systems, signal transmission encoding methods are used to provide the noise-shaping feature and to minimize distortion and error in the transmission channel. ? for 1000base-t, a special partial-response signaling met hod is used to provide the band-limiting feature for the transmission path. ? for 100base-tx, a simple slew-rate cont rol method is used to minimize emi. ? for 10base-t, pre-emphasis is used to extend the signal quality through the cable. 3.6 pll clock synthesizer the KSZ9031RNX generates 125 mhz, 25 mhz, and 10 mh z clocks for system timing. in ternal clocks are generated from the external 25 mhz crystal or reference clock. table 3-1: mdi/mdi-x pin mapping pin (rj-45 pair) mdi mdi-x 1000base-t 100base-t 10base-t 1000base-t 100base-t 10base-t txrxp/m_a (1, 2) a+/? tx+/? tx+/? b+/? rx+/? rx+/? txrxp/m_b (3, 6) b+/? rx+/? rx+/? a+/? tx+/? tx+/? txrxp/m_c (4, 5) c+/? not used not used d+/? not used not used txrxp/m_d (7, 8) d+/? not used not used c+/? not used not used
? 2016 microchip technology inc. ds00002117c-page 17 KSZ9031RNX 3.7 auto-negotiation the KSZ9031RNX conforms to the au to-negotiation protocol, defined in claus e 28 of the ieee 802.3 specification. auto-negotiation allows utp (unshielded twisted pair) link partners to select the highest common mode of operation. during auto-negotiation, link partners advertise capabilities across the utp link to each other, and then compare their own capabilities with those they received from their link partners. the highest speed and duplex setting that is common to the two link partners is selected as the operating mode. the following list shows the speed and duplex operation mode from highest-to-lowest: ? priority 1: 1000base-t, full-duplex ? priority 2: 1000base-t, half-duplex ? priority 3: 100base-tx, full-duplex ? priority 4: 100base-tx, half-duplex ? priority 5: 10base-t, full-duplex ? priority 6: 10base-t, half-duplex if auto-negotiation is not supported or the KSZ9031RNX link partner is forced to bypass auto-negotiation for 10base- t and 100base-tx modes, the KSZ9031RNX sets its operating mode by observing the input signal at its receiver. this is known as parallel detection, and allo ws the KSZ9031RNX to establish a link by listening for a fixed signal protocol in the absence of the auto-negotiation advertisement protocol. the auto-negotiation link-up process is shown in figure 3-3 . figure 3-3: auto-ne gotiation flow chart for 1000base-t mode, auto-negotiation is required and always used to establish a link. during 1000base-t auto- negotiation, the master and slave configur ation is first resolved between link pa rtners. then the link is established with the highest common capabilities between link partners. auto-negotiation is enabled by default after power-up or hardware reset. after that, auto-negotiation can be enabled or disabled through register 0h, bit [12]. if auto-negotiation is disabled, the speed is set by register 0h, bits [6, 13] and the duplex is set by register 0h, bit [8]. if the speed is changed on the fly, the link goes down and auto -negotiation and parallel detection initiate until a common speed between KSZ9031RNX and its link partner is re-established for a link. if the link is already established and ther e is no change of speed on the fly, the changes (for example, duplex and pause capabilities) will not take effect unless either auto-negotiation is restarted through register 0h, bit [9], or a link-down to link-up transition occurs (that is, disconnecting and reconnecting the cable). start auto-negotiation force link setting listen for 10base-t link pulses listen for 100base-tx idles attempt auto- negotiation link mode set bypass auto-negotiation and set link mode link mode set? parallel operation no yes yes no join flow
KSZ9031RNX ds00002117c-page 18 ? 2016 microchip technology inc. after auto-negotiation is completed, the li nk status is updated in register 1h, bit [2], and the link partner capabilities are updated in registers 5h, 6h, 8h, and ah. the auto-negotiation finite state machines use interval timers to manage the auto-negotiation process. the duration of these timers under normal operating conditions is summarized in table 3-2 . 3.8 10/100 mbps speeds only some applications require link-up to be limited to 10/100 mbps speeds only. after power-up/reset, the KSZ9031RNX can be restricted to aut o-negotiate and link-up to 10/100 mbps speeds only by programming the following register settings: 1. set register 0h, bit [6] = ?0? to remove 1000 mbps speed. 2. set register 9h, bits [9:8] = ?00? to remove auto-n egotiation advertisements for 1000 mbps full-/half-duplex. 3. write a ?1? to register 0h, bit [9], a self-clear ing bit, to force a rest art of auto-negotiation. auto-negotiation and 10base-t/100base-tx spee ds use only differential pairs a (p ins 2, 3) and b (pins 5, 6). differ- ential pairs c (pins 7, 8) and d (pins 10, 11) can be left as no connects. 3.9 rgmii interface the reduced gigabit media independent interface (rgmii) supports on-chip data-to-clock delay timing according to the rgmii version 2.0 specification, wit h programming options for external delay timing and to adjust and correct tx and rx timing paths. rgmii provides a common interface between rgmii phys and macs, and has the following key characteristics: ? pin count is reduced from 24 pins for the ieee gigabit m edia independent interface (gmii) to 12 pins for rgmii. ? all speeds (10 mbps, 100 mbps, and 1000 mbps ) are supported at both half- and full-duplex. ? data transmission and reception are independent and belong to separate signal groups. ? transmit data and receive data are each four bits wide, a nibble. in rgmii operation, the rgmii pins function as follows: ? the mac sources the transmit reference clock, txc, at 125 mhz for 1000 mbps, 25 mhz for 100 mbps, and 2.5 mhz for 10 mbps. ? the phy recovers and sources the receive reference clock, rxc, at 125 mhz for 1000 mbps, 25 mhz for 100 mbps, and 2.5 mhz for 10 mbps. ? for 1000base-t, the transmit data, txd[3:0], is pres ented on both edges of txc, and the received data, rxd[3:0], is clocked out on both edges of the recovered 125 mhz clock, rxc. ? for 10base-t/100base-tx, the mac holds tx_ctl low un til both phy and ma c operate at th e same speed. table 3-2: auto-negotiation timers auto-negotiation inter val timers time duration transmit burst interval 16 ms transmit pulse interval 68 s flp detect minimum time 17.2 s flp detect maximum time 185 s receive minimum burst interval 6.8 ms receive maximum burst interval 112 ms data detect minimum interval 35.4 s data detect maximum interval 95 s nlp test minimum interval 4.5 ms nlp test maximum interval 30 ms link loss time 52 ms break link time 1480 ms parallel detection wait time 830 ms link enable wait time 1000 ms
? 2016 microchip technology inc. ds00002117c-page 19 KSZ9031RNX during the speed transition, the receive clock is stretch ed on either a positive or negative pulse to ensure that no clock glitch is presented to the mac. ? tx_er and rx_er are combined with tx_en and rx_dv, respectively, to form tx_ctl and rx_ctl. these two rgmii control signals are va lid at the falling clock edge. after power-up or reset, the KSZ9031RNX is configured to rgmi i mode if the mode[3:0] strap-in pins are set to one of the rgmii mode capability options. see the strap-in options - KSZ9031RNX section. the KSZ9031RNX has the option to output a 125 mhz referenc e clock on the clk125_ndo pin. this clock provides a lower-cost reference clock alternative fo r rgmii macs that require a 125 mhz crystal or oscillator. the 125 mhz clock output is enabled after power-up or reset if the clk125_en strap-in pin is pulled high. 3.9.1 rgmii signal definition table 3-3 describes the rgmii signals. refer to the rgmii vers ion 2.0 specification for more detailed information. 3.9.2 rgmii signal diagram the KSZ9031RNX rgmii pin connections to the mac are shown in figure 3-4 . figure 3-4: KSZ9031RNX rgmii interface table 3-3: rgmii signal definition rgmii signal name (per spec) rgmii signal name (per KSZ9031RNX) pin type (with respect to phy) pin type (with respect to mac) description txc gtx_clk input output transmit reference clock (125mhz for 1000mbps, 25mhz for 100mbps, 2.5mhz for 10mbps) tx_ctl tx_en input output transmit control txd[3:0] txd[3:0] input output transmit data[3:0] rxc rx_clk output input receive reference clock (125 mhz for 1000 mbps, 25 mhz for 100 mbps, 2.5 mhz for 10 mbps) rx_ctl rx_dv output input receive control rxd[3:0] rxd[3:0] output input receive data[3:0] KSZ9031RNX gtx _clk tx _en txd[3:0] rx_clk rx _dv rxd [3:0] gmii ethernet mac txc tx _ctl txd[3:0] rxc rx _ctl rxd [3:0] r
KSZ9031RNX ds00002117c-page 20 ? 2016 microchip technology inc. 3.9.3 rgmii pad skew registers pad skew registers are available for all rgmii pins (clocks, control signals, and data bits) to provide programming options to adjust or correct the timing relationship for each rgmii pin. because rgmii is a source-synchronous bus interface, the timing relationship needs to be maintained only within the rgmii pin?s respective timing group. ? rgmii transmit timing group pins: gtx_clk, tx_en, txd[3:0] ? rgmii receive timing group pins: rx_clk, rx_dv, rxd[3:0] table 3-4 details the four registers located at mmd addr ess 2h that are provided for pad skew programming. the rgmii control signal s and data bits have 4-bit skew settings, while the rgmii clocks have 5-bit skew settings. each register bit is approximately a 0.06 ns step change . a single-bit decrement decreases the delay by approximately 0.06 ns, while a single-bit increment increas es the delay by approximately 0.06 ns. table 3-5 and ta b l e 3 - 6 list the approximate absolute delay for each pad skew (value) setting. table 3-4: rgmii pad skew registers address name description mode default mmd address 2h, register 4h ? rgmii control signal pad skew 2.4.15:8 reserved reserved rw 0000_0000 2.4.7:4 rx_dv pad skew rgmii rx_ctl output pad skew control (0.06 ns/ step) rw 0111 2.4.3:0 tx_en pad skew rgmii tx_ctl input pad skew control (0.06 ns/ step) rw 0111 mmd address 2h, register 5h ? rgmii rx data pad skew 2.5.15:12 rxd3 pad skew rgmii rxd3 output pad skew control (0.06 ns/ step) rw 0111 2.5.11:8 rxd2 pad skew rgmii rxd2 output pad skew control (0.06 ns/ step) rw 0111 2.5.7:4 rxd1 pad skew rgmii rxd1 output pad skew control (0.06 ns/ step) rw 0111 2.5.3:0 rxd0 pad skew rgmii rxd0 output pad skew control (0.06 ns/ step) rw 0111 mmd address 2h, register 6h ? rgmii tx data pad skew 2.6.15:12 txd3 pad skew rgmii txd3 input pad skew c ontrol (0.06 ns/step) rw 0111 2.6.11:8 txd2 pad skew rgmii txd2 input pad skew c ontrol (0.06 ns/step) rw 0111 2.6.7:4 txd1 pad skew rgmii txd1 input pad skew c ontrol (0.06 ns/step) rw 0111 2.6.3:0 txd0 pad skew rgmii txd0 input pad skew c ontrol (0.06 ns/step) rw 0111 mmd address 2h, register 8h ? rgmii clock pad skew 2.8.15:10 reserved reserved rw 0000_00 2.8.9:5 gtx_clk pad skew rgmii gtx_clk input pad skew control (0.06 ns/ step) rw 01_111 2.8.4:0 rx_clk pad skew rgmii rx_clk output pad skew control (0.06 ns/ step) rw 0_1111
? 2016 microchip technology inc. ds00002117c-page 21 KSZ9031RNX table 3-5: absolute delay for 5-bit pad skew setting pad skew value delay (ns) 0_0000 ?0.90 0_0001 ?0.84 0_0010 ?0.78 0_0011 ?0.72 0_0100 ?0.66 0_0101 ?0.60 0_0110 ?0.54 0_0111 ?0.48 0_1000 ?0.42 0_1001 ?0.36 0_1010 ?0.30 0_1011 ?0.24 0_1100 ?0.18 0_1101 ?0.12 0_1110 ?0.06 0_1111 no delay adjustment (default value) 1_0000 +0.06 1_0001 +0.12 1_0010 +0.18 1_0011 +0.24 1_0100 +0.30 1_0101 +0.36 1_0110 +0.42 1_0111 +0.48 1_1000 +0.54 1_1001 +0.60 1_1010 +0.66 1_1011 +0.72 1_1100 +0.78 1_1101 +0.84 1_1110 +0.90 1_1111 +0.96
KSZ9031RNX ds00002117c-page 22 ? 2016 microchip technology inc. when computing the rgmii timing relationships, delays along the entire data path must be aggregated to determine the total delay to be used for comparison between rgmii pins with in their respective timing group. for the transmit data path, total delay includes mac output delay, mac-to-phy pcb routing delay, and phy (KSZ9031RNX) input delay and skew setting (if any). for the receive data path, the total delay includes phy (KSZ9031RNX) output delay, phy-to-mac pcb routing delay, and mac input delay and skew setting (if any). as the default, after power-up or reset, the KSZ9031RNX rg mii timing conforms to the timing requirements in the rgmii version 2.0 specification for internal phy chip delay. for the transmit path (mac to KSZ9031RNX), the KSZ9031RNX does not add any delay locally at its gtx_clk, tx_en and txd[3:0] input pins, and expects the gtx_clk delay to be provided on-chip by the mac. if mac does not provide any delay or insufficient delay for the gtx_clk, the KSZ9031RNX has pad skew registers that can provide up to 1.38 ns on-chip delay. for the receive path (KSZ9031RNX to mac), the KSZ9031RNX adds 1.2ns typical delay to the rx_clk output pin with respect to rx_dv and rxd[3:0] output pins. if necessary, the KSZ9031RNX has pad skew registers that can adjust the rx_clk on-chip delay up to 2.58 ns from the 1.2 ns default delay. the above default rgmii timings imply: ? rx_clk clock skew is set by the KSZ9031RNX default register settings. ? gtx_clk clock skew is provided by the mac. ? no pcb delay is required for gtx_clk and rx_clk clocks. the following examples show how to read/write to mmd address 2h, register 8h for the rgmii gtx_clk and rx_clk skew settings. mmd register access is through the direct portal registers dh and eh. for more programming details, refer to the mmd registers section. ? read back value of mmd address 2h, register 8h. - write register 0xd = 0x0002 // select mmd device address 2h - write register 0xe = 0x0008 // select register 8h of mmd device address 2h - write register 0xd = 0x4002 // select regist er data for mmd device address 2h, register 8h - read register 0xe // read value of mmd device address 2h, register 8h table 3-6: absolute delay fo r 4-bit pad skew setting pad skew value delay (ns) 0000 ?0.42 0001 ?0.36 0010 ?0.30 0011 ?0.24 0100 ?0.18 0101 ?0.12 0110 ?0.06 0111 no delay adjustment (default value) 1000 +0.06 1001 +0.12 1010 +0.18 1011 +0.24 1100 +0.30 1101 +0.36 1110 +0.42 1111 +0.48
? 2016 microchip technology inc. ds00002117c-page 23 KSZ9031RNX ? write value 0x03ff (delay gtx_clk and rx_clk pad skews to their maximum values) to mmd address 2h, register 8h - write register 0xd = 0x0002 // select mmd device address 2h - write register 0xe = 0x0008 // select register 8h of mmd device address 2h - write register 0xd = 0x4002 // select regist er data for mmd device address 2h, register 8h - write register 0xe = 0x03ff // write value 0x03ff to mmd device address 2h, register 8h 3.9.4 rgmii in-band status the KSZ9031RNX provides in-band status to the mac duri ng the inter-frame gap when rx_dv is de-asserted. rgmii in-band status is always enabled after power-up. the in-band status is sent to the mac using the rxd[3:0] data pins, and is described in table 3-7 . 3.10 mii management (miim) interface the KSZ9031RNX supports the ieee 802.3 mii management in terface, also known as the management data input/ output (mdio) interface. this interface allows upper-layer devices to monitor and control the state of the KSZ9031RNX. an external device with miim capability is used to read t he phy status and/or configure the phy settings. more details about the miim interface can be found in clause 22.2.4 of the ieee 802.3 specification. the miim interface consists of the following: ? a physical connection that incorporates th e clock line (mdc) and the data line (mdio). ? a specific protocol that operates across the physical connection mentioned earlier, which allows an external con- troller to communicate with one or more KSZ9031RNX de vices. each KSZ9031RNX device is assigned a unique phy address between 0h and 7h by th e phyad[2:0] strapping pins. ? a 32-register address space for direct access to ieee-de fined registers and vendor-specific registers, and for indi- rect access to mmd addresses and registers. see the register map section. phy address 0h is supported as the unique phy address only; it is not supported as the broadcast phy address, which allows for a single write command to simultaneously program an identical phy register for two or more phy devices (for example, using phy address 0h to set register 0h to a value of 0x1940 to set bit [11] to a value of one to enable software power-down). instead, separate write commands are used to program each phy device. table 3-8 shows the mii management frame format for the KSZ9031RNX. 3.11 interrupt (int_n) the int_n pin is an optional interrupt signal that is used to inform the external controller that there has been a status update in the KSZ9031RNX phy register. bits [15:8] of regist er 1bh are the interrupt control bits that enable and dis- able the conditions for asserting the int_n signal. bits [7:0] of register 1bh are the interrupt status bits that indicate which interrupt conditions have occurred. the interrupt status bits are cleared after reading register 1bh. bit [14] of register 1fh sets the interrupt level to ac tive high or active low. the default is active low. table 3-7: rgmii in-band status rx_dv rxd3 rxd[2:1] rxd0 0 (valid only when rx_dv is low) duplex status 0 = half-duplex 1 = full-duplex rx_clk clock speed 00 = 2.5 mhz (10 mbps) 01 = 25 mhz (100 mbps) 10 = 125 mhz (1000 mbps) 11 = reserved link status 0 = link down 1 = link up table 3-8: mii management fram e format for the KSZ9031RNX preamble start of frame read/write op code phy address bits [4:0] reg address bits [4:0] ta data bits [15:0] idle read 32 1?s 01 10 00aaa rrrrr z0 dddddddd_dddddddd z write 32 1?s 01 01 00aaa rrrrr 10 dddddddd_dddddddd z
KSZ9031RNX ds00002117c-page 24 ? 2016 microchip technology inc. the mii management bus option gives the mac processo r complete access to the KSZ9031RNX control and status registers. additionally, an interrupt pin eliminates the need for the processor to poll the phy for status change. 3.12 led mode the KSZ9031RNX provides two programmable led output pi ns, led2 and led1, which are configurable to support two led modes. the led mode is configur ed by the led_mode strap-in (pin 41). it is latched at power-up/reset and is defined as follows: ? pull-up: single-led mode ? pull-down: tri-color dual-led mode each led output pin can directly drive an le d with a series resistor (typically 220 ? to 470 ? ). 3.12.1 single-led mode in single-led mode, the led2 pin indicates the link status wh ile the led1 pin indicates the activity status, as shown in table 3-9 . 3.12.2 tri-color dual-led mode in tri-color dual-led mode, the link and activity status ar e indicated by the led2 pin for 1000base-t; by the led1 pin for 100base-tx; and by both led2 and led1 pins, working in conjunction, for 10base-t. this is summarized in table 3-10 . table 3-9: single-led mode - pin definition led pin pin state led definition link/activity led2 h off link off l on link on (any speed) led1 h off no activity toggle blinking activity (rx, tx) table 3-10: tri-color dual-led mode - pin definition led pin (state) led pin (definition) link/activity led2 led1 led2 led1 h h off off link off l h on off 1000 link/no activity toggle h blinking off 1000 link/activity (rx, tx) h l off on 100 link/no activity h toggle off blinking 100 link/activity (rx, tx) l l on on 10 link/no activity toggle toggle blinking blinking 10 link/activity (rx, tx)
? 2016 microchip technology inc. ds00002117c-page 25 KSZ9031RNX 3.13 loopback mode the KSZ9031RNX supports the following loopback oper ations to verify analog and/or digital data paths. ? local (digital) loopback ? remote (analog) loopback 3.13.1 local (dig ital) loopback this loopback mode checks the rgmii transmit and receive dat a paths between KSZ9031RNX and external mac, and is supported for all three speeds (10/100/1000 mbps) at full-duplex. the loopback data path is shown in figure 3-5 . 1. rgmii mac transmits frames to KSZ9031RNX. 2. frames are wrapped around inside KSZ9031RNX. 3. KSZ9031RNX transmits frames back to rgmii mac. figure 3-5: local (digital) loopback the following programming steps and register settings are used for local loopback mode. for 1000 mbps loopback, 1. set register 0h, - bit [14] = 1 // enable local loopback mode - bits [6, 13] = 10 // select 1000 mbps speed - bit [12] = 0 // dis able auto-negotiation - bit [8] = 1 // select full-duplex mode 2. set register 9h, - bit [12] = 1 // enable mast er-slave manual configuration - bit [11] = 0 // select slave conf iguration (required for loopback mode) for 10/100 mbps loopback, 1. set register 0h, - bit [14] = 1 // enable local loopback mode - bits [6, 13] = 00 / 01 // se lect 10 mbps/100 mbps speed - bit [12] = 0 // dis able auto-negotiation - bit [8] = 1 // select full-duplex mode 3.13.2 remote (analog) loopback this loopback mode checks the line (differential pairs, tran sformer, rj-45 connector, et hernet cable) transmit and receive data paths between KSZ9031RNX and its link partner, and is supported for 1000base-t full-duplex mode only. the loopback data path is shown in figure 3-6 . 1. the gigabit phy link partner transmits frames to KSZ9031RNX. 2. frames are wrapped around inside KSZ9031RNX. 3. KSZ9031RNX transmits frames back to the gigabit phy link partner. pcs (digital) afe (analog) KSZ9031RNX rgmii rgmii mac
KSZ9031RNX ds00002117c-page 26 ? 2016 microchip technology inc. figure 3-6: remote (analog) loopback the following programming steps and register settings are used for remote loopback mode. 1. set register 0h, - bits [6, 13] = 10 // select 1000 mbps speed - bit [12] = 0 // dis able auto-negotiation - bit [8] = 1 // select full-duplex mode or just auto-negotiat e and link up at 1000base-t full-dupl ex mode with the link partner. 2. set register 11h, - bit [8] = 1 // enable remote loopback mode 3.14 linkmd ? cable diagnostic the linkmd function uses time domain reflectometry (t dr) to analyze the cabling plant for common cabling prob- lems, such as open circuits, short circuits, and impedance mismatches. linkmd operates by sending a pulse of known amplitude and duration down the selected differential pair, then analyzing the polarity and shape of the reflected signal to determine th e type of fault: open circuit for a positive/non-inverted ampli- tude reflection and short circuit for a negative/inverted amplit ude reflection. the time duration for the reflected signal to return provides the approximate distance to the cabling fault. the linkmd function processes this tdr information and presents it as a numerical value that can be translated to a cable distance. linkmd is initiated by accessing register 12h, the linkmd cable diagnostic register, in conjunction with register 1ch, the auto mdi/mdi-x register. the latter register is needed to disable the auto mdi/mdi-x function before running the linkmd test. additionally, a software reset (reg. 0h, bit [15] = 1) should be performed before and after running the linkmd test. the reset helps to ensure the KSZ9031RNX is in the normal operating stat e before and after the test. 3.15 nand tree support the KSZ9031RNX provides parametric nand tree support fo r fault detection between chip i/os and board. nand tree mode is enabled at power-up/reset with the mode[3:0] strap-in pins set to ?0100?. table 3-11 lists the nand tree pin order. table 3-11: nand tree test pin order for KSZ9031RNX pin description led2 input led1/pme_n1 input txd0 input txd1 input txd2 input txd3 input rj-45 rj-45 cat-5 (utp) KSZ9031RNX 1000base-t link partner afe (analog) pcs (digital) rgmii
? 2016 microchip technology inc. ds00002117c-page 27 KSZ9031RNX 3.16 power management the KSZ9031RNX incorporates a number of power-management modes and features that provide methods to consume less energy. these are discussed in the following sections. 3.16.1 energy-detect power-down mode energy-detect power-down (edpd) mode is used to further reduce the transceiv er power consumption when the cable is unplugged. it is enabled by writing a one to mmd address 1ch, register 23h, bi t [0], and is in effect when auto-nego- tiation mode is enabled and the cable is disconnected (no link). in edpd mode, the KSZ9031RNX shuts down all transceiver blocks, except for the transmitter and energy detect cir- cuits. power can be reduced further by extending the time interval between the transmissions of link pulses to check for the presence of a link partner. the periodic transmission of link pulses is needed to ensure the KSZ9031RNX and its link partner, when operating in the same low-power state and with auto mdi/mdi-x disabled, can wake up when the cable is connected between them. by defaul t, edpd mode is disabled after power-up. 3.16.2 software power-down mode this mode is used to power down the KSZ9031RNX device when it is not in use after power-up. software power-down (spd) mode is enabled by writing a one to register 0h, bit [11]. in the spd state, the KSZ9031RNX disables all internal functions, except for the mii m anagement interface. the KSZ9031RNX exits the spd state after a zero is written to reg- ister 0h, bit [11]. 3.16.3 chip powe r-down mode this mode provides the lowest power st ate for the KSZ9031RNX device when it is mounted on the board but not in use. chip power-down (cpd) mode is enabled after power-up/reset with the mode[3:0] strap-in pins set to ?0111?. the KSZ9031RNX exits cpd mode after a hardw are reset is applied to the reset_n pin (pin 42) with t he mode[3:0] strap- in pins set to an operating mode other than cpd. 3.17 wake-on-lan wake-on-lan (wol) is normally a mac-bas ed function to wake up a host system (for example, an ethernet end device, such as a pc) that is in standby power mode. wake -up is triggered by receiving and detecting a special packet (commonly referred to as the ?magic packet?) that is sent by the remote link partner. the KSZ9031RNX can perform the same wol function if the mac address of its associated ma c device is entered into the KSZ9031RNX phy registers for magic-packet detection. when the ksz 9031rnx detects the magic packet, it wa kes up the host by driving its power management event (pme) output pin low. by default, the wol function is disabled. it is enabled by setting the enabling bit and config uring the associated registers for the selected pme wake-up detection method. the KSZ9031RNX provides three methods to trigger a pme wake-up: ? magic-packet detection ?customized-pa cket detection ? link status change detection gtx_clk input tx_en input rx_dv input rx_clk input int_/pme_n2 input mdc input mdio input clk125_ndo output table 3-11: nand tree test pin order for KSZ9031RNX (continued) pin description
KSZ9031RNX ds00002117c-page 28 ? 2016 microchip technology inc. 3.17.1 magic-packet detection the magic packet?s frame format starts with 6 bytes of 0xff h and is followed by 16 repetitions of the mac address of its associated mac device (local mac device). when the magic packet is detected from its link pa rtner, the KSZ9031RNX asserts its pme output pin low. the following mmd address 2h registers are provided for magic-packet detection: ? magic-packet detection is enabled by writing a ?1? to mmd address 2h, register 10h, bit [6] ? the mac address (for the local mac device) is writt en to and stored in mmd address 2h, registers 11h ? 13h the KSZ9031RNX does no t generate the magic packet. the magic packe t must be provided by the external system. 3.17.2 customized-packet detection the customized packet has associated regi ster/bit masks to sele ct which byte, or bytes, of the first 64 bytes of the packet to use in the crc calculation. after the KSZ9031RNX receives the packet from its link partner, the selected bytes for the received packet are used to calculate the crc. the calculated crc is compared to the expected crc value that was previously written to and stored in the KSZ9031RNX phy registers. if there is a ma tch, the KSZ9031RNX asserts its pme output pin low. four customized packets are provided to support four types of wake-up scenarios. a dedicated set of registers is used to configure and enable each customized packet. the following mmd registers are provided for customized-packet detection: ? each of the four customized packets is enabled via mmd address 2h, register 10h, - bit [2] // for customized packets, type 0 - bit [3] // for customized packets, type 1 - bit [4] // for customized packets, type 2 - bit [5] // for customized packets, type 3 ? 32-bit expected crcs are written to and stored in: - mmd address 2h, registers 14h ? 15h // for customized packets, type 0 - mmd address 2h, registers 16h ? 17h // for customized packets, type 1 - mmd address 2h, registers 18h ? 19h // for customized packets, type 2 - mmd address 2h, registers 1ah ? 1bh // for customized packets, type 3 ? masks to indicate which of the first 64-byte s to use in the crc calculation are set in: - mmd address 2h, registers 1ch ? 1fh // for customized packets, type 0 - mmd address 2h, registers 20h ? 23h // for customized packets, type 1 - mmd address 2h, registers 24h ? 27h // for customized packets, type 2 - mmd address 2h, registers 28h ? 2bh // for customized packets, type 3
? 2016 microchip technology inc. ds00002117c-page 29 KSZ9031RNX 3.17.3 link status change detection if link status change detection is enabled, the KSZ9031RNX asserts its pme output pin low whenever there is a link status change using the following mmd address 2h registers bits and their enabled (1) or disabled (0) settings: ? mmd address 2h, register 10h, bit [0] // for link-up detection ? mmd address 2h, register 10h, bit [1] // for link-down detection the pme output signal is available on either led1/pme_n1 (pin 17) or int_n/pme_n2 (pin 38), and is selected and enabled using mmd address 2h, register 2h, bits [8] and [10], respectively. additionally, mmd address 2h, register 10h, bits [15:14] defines the out put functions for pins 17 and 38. the pme output is active low and requires a 1 k ? pull-up to the vddio supply. when asserted, the pme output is cleared by disabling the register bit that enabled the pme trigger source (ma gic packet, customized packet, link status change). 3.18 typical current/power consumption table 3-12 , table 3-13 , ta b l e 3 - 1 4 , and table 3-15 show the typical current consumption by the core (dvddl, avddl, avddl_pll), transceiver (avddh), and digital i/o (dvddh) supply pins, and the total typical power for the entire KSZ9031RNX device for various nominal operating voltage combinations. table 3-12: typical current/power consumption transceiver (3.3v), digital i/o (3.3v) condition 1.2v core (dvddl, avddl, avddl_pll) 3.3v transceiver (avddh) 3.3v digital i/o (dvddh) total chip power 1000base-t link-up (no traffic) 210 ma 67.4 ma 19.5 ma 538 mw 1000base-t full-duplex at 100% utilization 221 ma 66.3 ma 41.5 ma 621 mw 100base-tx link-up (no traffic) 63.6 ma 28.7 ma 13.9 ma 217 mw 100base-tx full-duplex at 100% utilization 63.8 ma 28.6 ma 17.2 ma 228 mw 10base-t link-up (no traffic) 7.1 ma 15.9 ma 11.5 ma 99 mw 10base-t full-duplex at 100% utilization 7.7 ma 28.6 ma 13.7 ma 149 mw software power-down mode (reg. 0h.11 = 1) 1.0 ma 4.2 ma 9.3 ma 46 mw table 3-13: typical current/power consumption transceiver (3.3v), digital i/o (1.8v) condition 1.2v core (dvddl, avddl, avddl_pll) 3.3v transceiver (avddh) 1.8v digital i/o (dvddh) total chip power 1000base-t link-up (no traffic) 210 ma 67.4 ma 11.2 ma 494 mw 1000base-t full-duplex at 100% utilization 221 ma 66.3 ma 23.6 ma 526 mw 100base-tx link-up (no traffic) 63.6 ma 28.7 ma 8.4 ma 186 mw 100base-tx full-duplex at 100% utilization 63.8 ma 28.6 ma 9.8 ma 189 mw 10base-t link-up (no traffic) 7.1 ma 15.9 ma 3.6 ma 67 mw 10base-t full-duplex at 100% utilization 7.7 ma 28.6 ma 5.6 ma 114 mw software power-down mode (reg. 0h.11 = 1) 1.0 ma 4.2 ma 5.5 ma 25 mw
KSZ9031RNX ds00002117c-page 30 ? 2016 microchip technology inc. note 3-1 2.5v avddh is recommended for commercial temperature range (0c to +70c) operation only. note 3-2 2.5v avddh is recommended for commercial temperature range (0c to +70c) operation only. table 3-14: typical current/power consumption transceiver (2.5v; note 3-1 ), digital i/o (2.5v) condition 1.2v core (dvddl, avddl, avddl_pll) 2.5v transceiver (avddh) 2.5v digital i/o (dvddh) total chip power 1000base-t link-up (no traffic) 210 ma 58.8 ma 14.7 ma 435 mw 1000base-t full-duplex at 100% utilization 221 ma 57.9 ma 31.5 ma 488 mw 100base-tx link-up (no traffic) 63.6 ma 24.9 ma 10.5 ma 165 mw 100base-tx full-duplex at 100% utilization 63.8 ma 24.9 ma 13.0 ma 171 mw 10base-t link-up (no traffic) 7.1 ma 11.5 ma 6.3 ma 53 mw 10base-t full-duplex at 100% utilization 7.7 ma 25.3 ma 9.0 ma 95 mw software power-down mode (reg. 0h.11 = 1) 1.0 ma 3.1 ma 6.7 ma 26 mw table 3-15: typical current/power consumption transceiver (2.5v; note 3-2 ), digital i/o (1.8v) condition 1.2v core (dvddl, avddl, avddl_pll) 2.5v transceiver (avddh) 1.8v digital i/o (dvddh) total chip power 1000base-t link-up (no traffic) 210 ma 58.8 ma 11.2 ma 419 mw 1000base-t full-duplex at 100% utilization 221 ma 57.9 ma 23.6 ma 452 mw 100base-tx link-up (no traffic) 63.6 ma 24.9 ma 8.4 ma 154 mw 100base-tx full-duplex at 100% utilization 63.8 ma 24.9 ma 9.8 ma 156 mw 10base-t link-up (no traffic) 7.1 ma 11.5 ma 3.6 ma 44 mw 10base-t full-duplex at 100% utilization 7.7 ma 25.3 ma 5.6 ma 83 mw software power-down mode (reg. 0h.11 = 1) 1.0 ma 3.1 ma 5.5 ma 19 mw
? 2016 microchip technology inc. ds00002117c-page 31 KSZ9031RNX 4.0 register descriptions this chapter describes the various co ntrol and status registers (csrs). 4.1 register map the register space within the KSZ9031RNX consists of two distinct areas. ? standard registers // direct register access ? mdio manageable device (mmd) registers // indirect register access the KSZ9031RNX supports the following standard registers. the KSZ9031RNX supports the following mmd device addresses and their associated register addresses, which make up the indirect mmd register s. these can be seen in ta b l e 4 - 2 . table 4-1: standard registers supported by KSZ9031RNX register number (hex) description ieee-defined registers 0h basic control 1h basic status 2h phy identifier 1 3h phy identifier 2 4h auto-negotiation advertisement 5h auto-negotiation link partner ability 6h auto-negotiation expansion 7h auto-negotiation next page 8h auto-negotiation link partner next page ability 9h 1000base-t control ah 1000base-t status bh - ch reserved dh mmd access ? control eh mmd access ? register/data fh extended status vendor-specific registers 10h reserved 11h remote loopback 12h linkmd cable diagnostic 13h digital pma/pcs status 14h reserved 15h rxer counter 16h - 1ah reserved 1bh interrupt control/status 1ch auto mdi/mdi-x 1dh - 1eh reserved 1fh phy control
KSZ9031RNX ds00002117c-page 32 ? 2016 microchip technology inc. table 4-2: mmd registers supported by KSZ9031RNX device address (hex) register address (hex) description 0h 3h an flp burst transmit ? lo 4h an flp burst transmit ? hi 1h 5ah 1000base-t link-up time control 2h 0h common control 1h strap status 2h operation mode strap override 3h operation mode strap status 4h rgmii control signal pad skew 5h rgmii rx data pad skew 6h rgmii tx data pad skew 8h gmii clock pad skew 10h wake-on-lan ? control 11h wake-on-lan ? magic packet, mac-da-0 12h wake-on-lan ? magic packet, mac-da-1 13h wake-on-lan ? magic packet, mac-da-2 14h wake-on-lan ? customized packet, type 0, expected crc 0 15h wake-on-lan ? customized packet, type 0, expected crc 1 16h wake-on-lan ? customized packet, type 1, expected crc 0 17h wake-on-lan ? customized packet, type 1, expected crc 1 18h wake-on-lan ? customized packet, type 2, expected crc 0 19h wake-on-lan ? customized packet, type 2, expected crc 1 1ah wake-on-lan ? customized packet, type 3, expected crc 0 1bh wake-on-lan ? customized packet, type 3, expected crc 1 1ch wake-on-lan ? customized packet, type 0, mask 0 1dh wake-on-lan ? customized packet, type 0, mask 1 1eh wake-on-lan ? customized packet, type 0, mask 2 1fh wake-on-lan ? customized packet, type 0, mask 3 20h wake-on-lan ? customized packet, type 1, mask 0 21h wake-on-lan ? customized packet, type 1, mask 1 22h wake-on-lan ? customized packet, type 1, mask 2 23h wake-on-lan ? customized packet, type 1, mask 3
? 2016 microchip technology inc. ds00002117c-page 33 KSZ9031RNX 4.2 standard registers standard registers provide direct read/writ e access to a 32-register address space, as defined in clause 22 of the ieee 802.3 specification. within this addre ss space, the first 16 registers (registers 0h to fh) are defined according to the ieee specification, while the remaining 16 registers (registers 10h to 1fh) are defined specific to the phy vendor. 2h 24h wake-on-lan ? customized packet, type 2, mask 0 25h wake-on-lan ? customized packet, type 2, mask 1 26h wake-on-lan ? customized packet, type 2, mask 2 27h wake-on-lan ? customized packet, type 2, mask 3 28h wake-on-lan ? customized packet, type 3, mask 0 29h wake-on-lan ? customized packet, type 3, mask 1 2ah wake-on-lan ? customized packet, type 3, mask 2 2bh wake-on-lan ? customized packet, type 3, mask 3 1ch 4h analog control 4 23h edpd control table 4-3: ieee-defined register descriptions address name description mode note 4-1 default register 0h ? basic control 0.15 reset 1 = software phy reset 0 = normal operation this bit is self-cleared after a ?1? is written to it. rw/sc 0 0.14 loopback 1 = loopback mode 0 = normal operation rw 0 0.13 speed select (lsb) [0.6, 0.13] [1,1] = reserved [1,0] = 1000 mbps [0,1] = 100 mbps [0,0] = 10 mbps this bit is ignored if auto-negotiation is enabled (reg. 0.12 = 1). rw 0 0.12 auto-negoti- ation enable 1 = enable auto-negotiation process 0 = disable auto-negotiation process if enabled, auto-negotiati on result overrides set- tings in reg. 0.13, 0.8 and 0.6. if disabled, auto mdi-x is also automatically dis- abled. use register 1ch to set mdi/mdi-x. rw 1 0.11 power-down 1 = power - down mode 0 = normal operation when this bit is set to ?1?, the link-down status might not get updated in th e phy register. software should note link is down and should not rely on the phy register link status. after this bit is changed from ?1? to ?0?, an internal global reset is automatically generated. wait a min- imum of 1 ms before read/write access to the phy registers. rw 0 table 4-2: mmd registers suppor ted by KSZ9031RNX (continued) device address (hex) register address (hex) description
KSZ9031RNX ds00002117c-page 34 ? 2016 microchip technology inc. 0.10 isolate 1 = electrical is olation of phy from rgmii 0 = normal operation rw 0 0.9 restart auto- negotiation 1 = restart auto-negotiation process 0 = normal operation this bit is self-cleared after a ?1? is written to it. rw/sc 0 0.8 duplex mode 1 = full-duplex 0 = half-duplex rw 1 0.7 reserved reserved rw 0 0.6 speed select (msb) [0.6, 0.13] [1,1] = reserved [1,0] = 1000 mbps [0,1] = 100 mbps [0,0] = 10 mbps this bit is ignored if auto-negotiation is enabled (reg. 0.12 = 1). rw set by mode[3:0] strapping pins. see the strap-in options - KSZ9031RNX section for details. 0.5:0 reserved reserved ro 00_0000 register 1h - basic status 1.15 100base-t4 1 = t4 capable 0 = not t4 capable ro 0 1.14 100base-tx full-duplex 1 = capable of 100 mbps full-duplex 0 = not capable of 100 mbps full-duplex ro 1 1.13 100base-tx half-duplex 1 = capable of 100 mbps half-duplex 0 = not capable of 100 mbps half-duplex ro 1 1.12 10base-t full-duplex 1 = capable of 10 mbps full-duplex 0 = not capable of 10 mbps full-duplex ro 1 1.11 10base-t half-duplex 1 = capable of 10 mbps half-duplex 0 = not capable of 10 mbps half-duplex ro 1 1.10:9 reserved reserved ro 00 1.8 extended status 1 = extended status info in reg. 15h. 0 = no extended status info in reg. 15h. ro 1 1.7 reserved reserved ro 0 1.6 no preamble 1 = preamble suppression 0 = normal preamble ro 1 1.5 auto-negoti- ation com- plete 1 = auto-negotiation process completed 0 = auto-negotiation process not completed ro 0 1.4 remote fault 1 = remote fault 0 = no remote fault ro/lh 0 1.3 auto-negoti- ation ability 1 = can perform auto-negotiation 0 = cannot perform auto-negotiation ro 1 1.2 link status 1 = link is up 0 = link is down ro/ll 0 1.1 jabber detect 1 = jabber detected 0 = jabber not detected (default is low) ro/lh 0 1.0 extended capability 1 = supports extended capability registers ro 1 register 2h - phy identifier 1 table 4-3: ieee-defined regist er descriptions (continued) address name description mode note 4-1 default
? 2016 microchip technology inc. ds00002117c-page 35 KSZ9031RNX 2.15:0 phy id number assigned to bits [3:18] of the organizationally unique identifier (oui). kendin communication?s oui is 0010a1h. ro 0022h register 3h - phy identifier 2 3.15:10 phy id number assigned to bits [19:24] of the organizationally unique identifier (oui). kendin communication?s oui is 0010a1h. ro 0001_01 3.9:4 model number six-bit manufacturer?s model number ro 10_0010 3.3:0 revision number four-bit manufacturer?s revision number ro indicates silicon revision register 4h - auto-negotiation advertisement 4.15 next page 1 = next page capable 0 = no next page capability rw 0 4.14 reserved reserved ro 0 4.13 remote fault 1 = remote fault supported 0 = no remote fault rw 0 4.12 reserved reserved ro 0 4.11:10 pause [4.11, 4.10] [0,0] = no pause [1,0] = asymmetric pause (link partner) [0,1] = symmetric pause [1,1] = symmetric and asymmetric pause (local device) rw 00 4.9 100base-t4 1 = t4 capable 0 = no t4 capability ro 0 4.8 100base-tx full-duplex 1 = 100 mbps full-duplex capable 0 = no 100 mbps full-duplex capability rw 1 4.7 100base-tx half-duplex 1 = 100 mbps half-duplex capable 0 = no 100 mbps half-duplex capability rw 1 4.6 10base-t full-duplex 1 = 10 mbps full-duplex capable 0 = no 10 mbps full-duplex capability rw 1 4.5 10base-t half-duplex 1 = 10 mbps half-duplex capable 0 = no 10 mbps half-duplex capability rw 1 4.4:0 selector field [00001] = ieee 802.3 rw 0_0001 register 5h - auto-negotia tion link partner ability 5.15 next page 1 = next page capable 0 = no next page capability ro 0 5.14 acknowledge 1 = link code word received from partner 0 = link code word not yet received ro 0 5.13 remote fault 1 = remote fault detected 0 = no remote fault ro 0 5.12 reserved reserved ro 0 table 4-3: ieee-defined regist er descriptions (continued) address name description mode note 4-1 default
KSZ9031RNX ds00002117c-page 36 ? 2016 microchip technology inc. 5.11:10 pause [5.11, 5.10] [0,0] = no pause [1,0] = asymmetric pause (link partner) [0,1] = symmetric pause [1,1] = symmetric and asymmetric pause (local device) rw 00 5.9 100base-t4 1 = t4 capable 0 = no t4 capability ro 0 5.8 100base-tx full-duplex 1 = 100 mbps full-duplex capable 0 = no 100 mbps full-duplex capability ro 0 5.7 100base-tx half-duplex 1 = 100 mbps half-duplex capable 0 = no 100 mbps half-duplex capability ro 0 5.6 10base-t full-duplex 1 = 10 mbps full-duplex capable 0 = no 10 mbps full-duplex capability ro 0 5.5 10base-t half-duplex 1 = 10 mbps half-duplex capable 0 = no 10 mbps half-duplex capability ro 0 5.4:0 selector field [00001] = ieee 802.3 ro 0_0000 register 6h - auto-n egotiation expansion 6.15:5 reserved reserved ro 0000_0000_000 6.4 parallel detection fault 1 = fault detected by parallel detection 0 = no fault detected by parallel detection ro/lh 0 6.3 link partner next page able 1 = link partner has next page capability 0 = link partner does not have next page capability ro 0 6.2 next page able 1 = local device has next page capability 0 = local device does not have next page capabil- ity ro 1 6.1 page received 1 = new page received 0 = new page not received ro/lh 0 6.0 link partner auto-negoti- ation able 1 = link partner has auto-negotiation capability 0 = link partner does not have auto-negotiation capability ro 0 register 7h - auto-n egotiation next page 7.15 next page 1 = additional next pages will follow 0 = last page rw 0 7.14 reserved reserved ro 0 7.13 message page 1 = message page 0 = unformatted page rw 1 7.12 acknowl- edge2 1 = will comply with message 0 = cannot comply with message rw 0 7.11 toggle 1 = previous value of the transmitted link code word equaled logic one 0 = logic zero ro 0 7.10:0 message field 11-bit wide field to encode 2048 messages rw 000_0000_0001 register 8h - link partner next page ability table 4-3: ieee-defined regist er descriptions (continued) address name description mode note 4-1 default
? 2016 microchip technology inc. ds00002117c-page 37 KSZ9031RNX 8.15 next page 1 = additional next pages will follow 0 = last page ro 0 8.14 acknowledge 1 = successf ul receipt of link word 0 = no successful re ceipt of link word ro 0 8.13 message page 1 = message page 0 = unformatted page ro 0 8.12 acknowl- edge2 1 = able to act on the information 0 = not able to act on the information ro 0 8.11 toggle 1 = previous value of transmitted link code word equal to logic zero 0 = previous value of transmitted link code word equal to logic one ro 0 8.10:0 message field ? ro 000_0000_0000 register 9h ? 1000base-t control 9.15:13 test mode bits transmitter test mode operations [9.15:13] mode [000] normal operation [001] test mode 1 ?transmit waveform test [010] test mode 2 ?transmit jitter test in master mode [011] test mode 3 ?transmit jitter test in slave mode [100] test mode 4 ?transmitter distortion test [101] reserved, operations not identified [110] reserved, operations not identified [111] reserved, operat ions not identified to enable 1000base-t test mode: 1) set register 0h = 0x014 0 to disable auto-negoti- ation and select 1000 mbps speed. 2) set register 9h, bits [15:13] = 001, 010, 011, or 100 to select one of the 1000base-t test modes. after the above settings, the test waveform for the selected test mode is tr ansmitted onto each of the 4 differential pairs. no link partner is needed. rw 000 9.12 master-slave manual con- figuration enable 1 = enable master - slave manual configuration value 0 = disable master - slave manual configuration value rw 0 9.11 master-slave manual con- figuration value 1 = configure phy as master during master - slave negotiation 0 = configure phy as slave during master - slave negotiation this bit is ignored if master - slave manual configu- ration is disabled (reg. 9.12 = 0). rw 0 9.10 port type 1 = indicate the pref erence to operate as multi-port device (master) 0 = indicate the preference to operate as single - port device (slave) this bit is valid only if master - slave manual config- uration is disabled (reg. 9.12 = 0). rw 0 table 4-3: ieee-defined regist er descriptions (continued) address name description mode note 4-1 default
KSZ9031RNX ds00002117c-page 38 ? 2016 microchip technology inc. 9.9 1000base-t full-duplex 1 = advertise phy is 1000base-t full-duplex capable 0 = advertise phy is no t 1000base-t fu ll-duplex capable rw 1 9.8 1000base-t half-duplex 1 = advertise phy is 1000base-t half-duplex capable 0 = advertise phy is no t 1000base-t hal f-duplex capable rw set by mode[3:0] strapping pins. see the strap-in options - KSZ9031RNX section for details. 9.7:0 reserved write as 0, ignore on read ro ? register ah ? 1000base-t status a.15 master-slave configura- tion fault 1 = master-slave configuration fault detected 0 = no master - slave configuration fault detected ro/lh/sc 0 a.14 master-slave configura- tion resolu- tion 1 = local phy configuration resolved to master 0 = local phy configuration resolved to slave ro 0 a.13 local receiver status 1 = local receiver ok (loc_rcvr_status = 1) 0 = local receiver not ok (loc_rcvr_status = 0) ro 0 a.12 remote receiver status 1 = remote receiver ok (rem_rcvr_status = 1) 0 = remote receiver not ok (rem_rcvr_status = 0) ro 0 a.11 link partner 1000base-t full-duplex capability 1 = link partner is capable of 1000base-t full- duplex 0 = link partner is not capable of 1000base-t full-duplex ro 0 a.10 link partner 1000base-t half-duplex capability 1 = link partner is capable of 1000base-t half- duplex 0 = link partner is not capable of 1000base-t half-duplex ro 0 a.9:8 reserved reserved ro 00 a.7:0 idle error count cumulative count of erro rs detected when receiver is receiving idles and pma_txmode.indicate = send_n. the counter is incremented every symbol period that rxerror_status = error. ro/sc 0000_0000 register dh - mmd access ? control d.15:14 mmd ? operation mode for the selected mmd device address (bits [4:0] of this register), these two bits select one of the fol- lowing register or data operations and the usage for mmd access ? register/data (reg. eh). 00 = register 01 = data, no post increment 10 = data, post increment on reads and writes 11 = data, post increment on writes only rw 00 d.13:5 reserved reserved rw 00_0000_000 table 4-3: ieee-defined regist er descriptions (continued) address name description mode note 4-1 default
? 2016 microchip technology inc. ds00002117c-page 39 KSZ9031RNX note 4-1 rw = read/write; ro = read only; sc = self-cleared; lh = latch high; ll = latch low. d.4:0 mmd ? device address these five bits set the mmd device address. rw 0_0000 register eh - mmd access ? register/data e.15:0 mmd ? register/ data for the selected mmd device address (reg. dh, bits [4:0]), when reg. dh, bits [15:14] = 00, this register contains the read/write register address for the mmd device address . otherwise, this regi ster contains the read/write data value for the mmd device address and its selected register address. see also reg. dh, bits [15:14], for descriptions of post increment reads and writes of this register for data operation. rw 0000_0000_0000_00 00 register fh ? extended status f.15 1000base-x full-duplex 1 = phy can perform 1000base-x full-duplex 0 = phy cannot perform 1000base-x full-duplex ro 0 f.14 1000base-x half-duplex 1 = phy can perform 1000base-x half-duplex 0 = phy cannot perform 1000base-x half-duplex ro 0 f.13 1000base-t full-duplex 1 = phy can perform 1000base-t full-duplex 0 = phy cannot perfo rm 1000base-t full-duplex ro 1 f.12 1000base-t half-duplex 1 = phy can perform 1000base-t half-duplex 0 = phy cannot perfo rm 1000base-t half-duplex ro 1 f.11:0 reserved ignore when read ro ? table 4-4: vendor-specific register descriptions address name description mode note 4-1 default register 11h ? remote loopback 11.15:9 reserved reserved rw 0000_000 11.8 remote loopback 1 = enable remote loopback 0 = disable remote loopback rw 0 11.7:1 reserved reserved rw 1111_010 11.0 reserved reserved ro 0 register 12h ? linkmd ? cable diagnostic 12.15 cable diagnostic te s t e n a b l e write value: 1 = enable cable diagnostic test. after test has completed, this bit is self-cleared. 0 = disable cable diagnostic test. read value: 1 = cable diagnostic test is in progress. 0 = indicates cable diagnostic test (if enabled) has completed and the status information is valid for read. rw/sc 0 12.14 reserved this bit should always be set to ?0?. rw 0 table 4-3: ieee-defined regist er descriptions (continued) address name description mode note 4-1 default
KSZ9031RNX ds00002117c-page 40 ? 2016 microchip technology inc. 12.13:12 cable diagnostic te s t p a i r these two bits select the differential pair for testing: 00 = differential pair a (pins 2, 3) 01 = differential pair b (pins 5, 6) 10 = differential pair c (pins 7, 8) 11 = differential pair d (pins 10, 11) rw 00 12.11:10 reserved these two bits should always be set to ?00?. rw 00 12.9:8 cable diagnostic status these two bits represent the test result for the selected differential pair in bits [13:12] of this regis- ter. 00 = normal cable condition (no fault detected) 01 = open cable fault detected 10 = short cable fault detected 11 = reserved ro 00 12.7:0 cable diagnostic fault data for the open or short cable fault detected in bits [9:8] of this register, this 8-bit value represents the distance to the cable fault. ro 0000_0000 register 13h ? digital pma/pcs status 13.15:3 reserved reserved ro/lh 0000_0000_0000_0 13.2 1000base-t link status 1000base-t link status 1 = link status is ok 0 = link status is not ok ro 0 13.1 100base-tx link status 100base-tx link status 1 = link status is ok 0 = link status is not ok ro 0 13.0 reserved reserved ro 0 register 15h ? rxer counter 15.15:0 rxer counter receive error counter for symbol error frames ro/rc 0000_0000_0000_00 00 register 1bh ? interrupt control/status 1b.15 jabber inter- rupt enable 1 = enable jabber interrupt 0 = disable jabber interrupt rw 0 1b.14 receive error inter- rupt enable 1 = enable receive error interrupt 0 = disable receive error interrupt rw 0 1b.13 page received interrupt enable 1 = enable page received interrupt 0 = disable page received interrupt rw 0 1b.12 parallel detect fault interrupt enable 1 = enable parallel detect fault interrupt 0 = disable parallel detect fault interrupt rw 0 1b.11 link partner acknowl- edge inter- rupt enable 1 = enable link partner acknowledge interrupt 0 = disable link partner acknowledge interrupt rw 0 1b.10 link-down interrupt enable 1 = enable link-down interrupt 0 = disable link-down interrupt rw 0 table 4-4: vendor-specific register descriptions (continued) address name description mode note 4-1 default
? 2016 microchip technology inc. ds00002117c-page 41 KSZ9031RNX 1b.9 remote fault interrupt enable 1 = enable remote fault interrupt 0 = disable remote fault interrupt rw 0 1b.8 link-up interrupt enable 1 = enable link-up interrupt 0 = disable link-up interrupt rw 0 1b.7 jabber inter- rupt 1 = jabber occurred 0 = jabber did not occur ro/rc 0 1b.6 receive error inter- rupt 1 = receive error occurred 0 = receive error did not occur ro/rc 0 1b.5 page receive interrupt 1 = page receive occurred 0 = page receive did not occur ro/rc 0 1b.4 parallel detect fault interrupt 1 = parallel detect fault occurred 0 = parallel detect fault did not occur ro/rc 0 1b.3 link partner acknowl- edge inter- rupt 1 = link partner acknowledge occurred 0 = link partner acknowledge did not occur ro/rc 0 1b.2 link-down interrupt 1 = link-down occurred 0 = link-down did not occur ro/rc 0 1b.1 remote fault interrupt 1 = remote fault occurred 0 = remote fault did not occur ro/rc 0 1b.0 link-up interrupt 1 = link-up occurred 0 = link-up did not occur ro/rc 0 register 1ch ? auto mdi/mdi-x 1c.15:8 reserved reserved rw 0000_0000 1c.7 mdi set when swap-off (bit [6] of this register) is asserted (1), 1 = phy is set to operate as mdi mode 0 = phy is set to operate as mdi-x mode this bit has no function when swap-off is de-asserted (0). rw 0 1c.6 swap-off 1 = disable auto mdi/mdi-x function 0 = enable auto mdi/mdi-x function rw 0 1c.5:0 reserved reserved rw 00_0000 register 1fh ? phy control 1f.15 reserved reserved rw 0 1f.14 interrupt level 1 = interrupt pin active high 0 = interrupt pin active low rw 0 1f.13:12 reserved reserved rw 00 1f.11:10 reserved reserved ro/lh/rc 00 1f.9 enable jabber 1 = enable jabber counter 0 = disable jabber counter rw 1 1f.8:7 reserved reserved rw 00 table 4-4: vendor-specific register descriptions (continued) address name description mode note 4-1 default
KSZ9031RNX ds00002117c-page 42 ? 2016 microchip technology inc. note 4-1 rw = read/write; ro = read only; sc = self-cleared; rc = read-cleared; lh = latch high. 1f.6 speed status 1000base-t 1 = indicate chip final sp eed status at 1000base-t ro 0 1f.5 speed status 100base-tx 1 = indicate chip final sp eed status at 100base-tx ro 0 1f.4 speed status 10base-t 1 = indicate chip final speed status at 10base-t ro 0 1f.3 duplex status indicate chip duplex status 1 = full-duplex 0 = half-duplex ro 0 1f.2 1000base-t master/slave status indicate chip master/slave status 1 = 1000base-t master mode 0 = 1000base-t slave mode ro 0 1f.1 reserved reserved rw 0 1f.0 link status check fail 1 = fail 0 = not failing ro 0 table 4-4: vendor-specific register descriptions (continued) address name description mode note 4-1 default
? 2016 microchip technology inc. ds00002117c-page 43 KSZ9031RNX 4.3 mmd registers mmd registers provide indirect read/write access to up to 32 mmd device addresses with each device supporting up to 65,536 16-bit registers, as defined in clause 22 of the ieee 802.3 specification. the KSZ9031RNX, however, uses only a small fraction of the available registers. see the register map section for a list of supported mmd device addresses and their associated register addresses. the following two standard registers serve as the porta l registers to access the indirect mmd registers. ? standard register dh ? mmd access ? control ? standard register eh ? mmd access ? register/data note 4-1 rw = read/write. examples: mmd register write write mmd - device address 2h, register 10h = 0001h to enable link-up detection to trigger pme for wol. 1. write register dh with 0002h // set up register address for mmd ? device address 2h. 2. write register eh with 0010h // select register 10h of mmd ? device address 2h. 3. write register dh with 4002h // select register data for mmd ? device address 2h, register 10h. 4. write register eh with 0001h // write value 0001h to mmd ? device address 2h, register 10h. mmd register read read mmd - device address 2h, register 11 h ? 13h for the magic packet?s mac address. 1. write register dh with 0002h // set up register address for mmd ? device address 2h. 2. write register eh with 0011h // select register 11h of mmd ? device address 2h. 3. write register dh with 8002h // select register data for mmd ? device address 2h, register 11h. 4. read register eh // read data in mmd ? device address 2h, register 11h. 5. read register eh // read data in mmd ? device address 2h, register 12h. 6. read register eh // read data in mmd ? device address 2h, register 13h. table 4-5: mmd portal registers address name description mode note 4-1 default register dh - mmd access ? control d.15:14 mmd - operation mode for the selected mmd devic e address (bits [4:0] of this register), these two bits select one of the fol- lowing register or data operations and the usage for mmd access ? register/data (reg. eh). 00 = register 01 = data, no post increment 10 = data, post increment on reads and writes 11 = data, post increment on writes only rw 00 d.13:5 reserved reserved rw 00_0000_000 d.4:0 mmd ? device address these five bits set the mmd device address rw 0_0000 register eh - mmd access ? register/data e.15:0 mmd ? register/ data for the selected mmd de vice address (reg. dh, bits [4:0]), when reg. dh, bits [15:14] = 00, this register contains the read/write register address for the mmd device address. otherwise, this register contains the read/write data value for the mmd device address and its selected register address. see also register dh, bits [15:14] descriptions for post increment reads and writes of this register for data operation. rw 0000_0000_ 0000_0000
KSZ9031RNX ds00002117c-page 44 ? 2016 microchip technology inc. table 4-6: mmd register descriptions address name description mode note 4-1 default mmd address 0h, register 3h ? an flp burst transmit ? lo 0.3.15:0 an flp burst trans- mit ? lo this register and the following register set the auto-negotiation flp burst transmit timing. the same timing must be set for both registers. 0x4000 = select 8 ms interval timing (default) 0x1a80 = select 16 ms interval timing all other values are reserved. rw 0x4000 mmd address 0h, register 4h ? an flp burst transmit ? hi 0.4.15:0 an flp burst trans- mit ? hi this register and the previous register set the auto- negotiation flp burst transmit timing. the same timing must be set for both registers. 0x0003 = select 8 ms interval timing (default) 0x0006 = select 16 ms interval timing all other values are reserved. rw 0x0003 mmd address 1h, register 5ah ? 1000base-t link-up time control 1.5a.8:4 reserved reserved rw 1_0000 1.5a.3:1 1000base-t link-up time when the link partner is another ksz9031 device, the 1000base-t lin k-up time can be long. these three bits provide an optional setting to reduce the 1000base-t link-up time. 100 = default power-up setting 011 = optional setting to reduce link-up time when the link partner is a ksz9031 device. all other settings are reserved and should not be used. the optional setting is safe to use with any link partner. note: read/write access to this register bit is avail- able only when reg. 0h is set to 0x2100 to disable auto-negotiation and force 100base-tx mode. rw 100 1.5a.0 reserved reserved rw 0 mmd address 2h, register 0h ? common control 2.0.15:5 reserved reserved rw 0000_0000_000 2.0.4 led mode override override strap-in for led_mode 1 = single-led mode 0 = tri-color dual-led mode this bit is write-only and always reads back a value of ?0?. the updated value is reflected in bit [3] of this register. wo 0 2.0.3 led mode led_mode status 1 = single-led mode 0 = tri-color dual-led mode ro set by led_mode strapping pin. see the strap-in options - KSZ9031RNX section for details. can be updated by bit [4] of this register after reset. 2.0.2 reserved reserved rw 0
? 2016 microchip technology inc. ds00002117c-page 45 KSZ9031RNX 2.0.1 clk125_en status override strap-in for clk125_en 1 = clk125_en strap-in is enabled 0 = clk125_en strap-in is disabled rw set by clk125_en strapping pin. see the strap-in options - KSZ9031RNX section for details. 2.0.0 reserved reserved rw 0 mmd address 2h, register 1h ? strap status 2.1.15:8 reserved reserved ro 0000_0000 2.1.7 led_mode strap-in status strap to 1 = single-led mode 0 = tri-color dual-led mode ro set by led_mode strapping pin. see the strap-in options - KSZ9031RNX section for details. 2.1.6 reserved reserved ro 0 2.1.5 clk125_en strap-in status strap to 1 = clk125_en strap-in is enabled 0 = clk125_en strap-in is disabled ro set by clk125_en strapping pin. see the strap-in options - KSZ9031RNX section for details. 2.1.4:3 reserved reserved ro 00 2.1.2:0 phyad[2:0] strap-in value strap-in value for phy address bits [4:3] of phy address are always set to ?00?. ro set by phyad[2:0] strapping pin. see the strap-in options - KSZ9031RNX section for details. mmd address 2h, register 2h ? operation mode strap override 2.2.15 rgmii all capabilities override 1 = override strap-in for rgmii to advertise all capabilities rw set by mode[3:0] strapping pin. see the strap-in options - KSZ9031RNX section for details. 2.2.14 rgmii no 1000bt_hd override 1 = override strap-in for rgmii to advertise all capabilities except 1000base-t half-duplex rw 2.2.13 rgmii 1000bt_h/ fd only override 1 = override strap-in for rgmii to advertise 1000base-t full- and half-duplex only rw 2.2.12 rgmii 1000bt_fd only over- ride 1 = override strap-in for rgmii to advertise 1000base-t full-duplex only rw 2.2.11 reserved reserved rw 0 2.2.10 pme_n2 output enable for int_n/pme_n2 (pin 38), 1 = enable pme output 0 = disable pme output this bit works in conjunction with mmd address 2h, reg. 10h, bits [15:14] to define the output for pin 38. rw 0 table 4-6: mmd register d escriptions (continued) address name description mode note 4-1 default
KSZ9031RNX ds00002117c-page 46 ? 2016 microchip technology inc. 2.2.9 reserved reserved rw 0 2.2.8 pme_n1 output enable for led1/pme_n1 (pin 17), 1 = enable pme output 0 = disable pme output this bit works in conjunction with mmd address 2h, reg. 10h, bits [15:14] to define the output for pin 17. rw 0 2.2.7 chip power- down override 1 = override strap-in for chip power-down mode rw set by mode[3:0] strapping pin. see the strap-in options - KSZ9031RNX section for details. 2.2.6:5 reserved reserved rw 00 2.2.4 nand tree override 1 = override strap-in for nand tree mode rw set by mode[3:0] strapping pin. see the strap-in options - KSZ9031RNX section for details. 2.2.3:0 reserved reserved rw 0000 mmd address 2h, register 3h ? operation mode strap status 2.3.15 rgmii all capabilities strap-in status 1 = strap to rgmii to advertise all capabilities ro set by mode[3:0] strapping pin. see the strap-in options - KSZ9031RNX section for details. 2.3.14 rgmii no 1000bt_hd strap-in status 1 = strap to rgmii to advertise all capabilities except 1000base- t half-duplex ro 2.3.13 rgmii only 1000bt_h/ fd strap-in status 1 = strap to rgmii to advertise 1000base-t full - and half-duplex only ro 2.3.12 rgmii only 1000bt_fd strap-in status 1 = strap to rgmii to advertise 1000base-t full- duplex only ro 2.3.11:8 reserved reserved ro 0000 2.3.7 chip power- down strap- in status 1 = strap to chip power-down mode ro set by mode[3:0] strapping pin. see the strap-in options - KSZ9031RNX section for details. 2.3.6:5 reserved reserved ro 00 table 4-6: mmd register d escriptions (continued) address name description mode note 4-1 default
? 2016 microchip technology inc. ds00002117c-page 47 KSZ9031RNX 2.3.4 nand tree strap-in status 1 = strap to nand tree mode ro set by mode[3:0] strapping pin. see the strap-in options - KSZ9031RNX section for details. 2.3.3:0 reserved reserved ro 0000 mmd address 2h, register 4h ? rgmii control signal pad skew 2.4.15:8 reserved reserved rw 0000_0000 2.4.7:4 rx_dv pad skew rgmii rx_ctl output pad skew control (0.06 ns/ step) rw 0111 2.4.3:0 tx_en pad skew rgmii tx_ctl input pad skew control (0.06 ns/ step) rw 0111 mmd address 2h, register 5h ? rgmii rx data pad skew 2.5.15:12 rxd3 pad skew rgmii rxd3 output pad skew control (0.06 ns/ step) rw 0111 2.5.11:8 rxd2 pad skew rgmii rxd2 output pad skew control (0.06 ns/ step) rw 0111 2.5.7:4 rxd1 pad skew rgmii rxd1 output pad skew control (0.06 ns/ step) rw 0111 2.5.3:0 rxd0 pad skew rgmii rxd0 output pad skew control (0.06 ns/ step) rw 0111 mmd address 2h, register 6h ? rgmii tx data pad skew 2.6.15:12 txd3 pad skew rgmii txd3 input pad skew c ontrol (0.06 ns/step) rw 0111 2.6.11:8 txd2 pad skew rgmii txd2 input pad skew c ontrol (0.06 ns/step) rw 0111 2.6.7:4 txd1 pad skew rgmii txd1 input pad skew c ontrol (0.06 ns/step) rw 0111 2.6.3:0 txd0 pad skew rgmii txd0 input pad skew c ontrol (0.06 ns/step) rw 0111 mmd address 2h, register 8h ? rgmii clock pad skew 2.8.15:10 reserved reserved rw 0000_00 2.8.9:5 gtx_clk pad skew rgmii gtx_clk input pad skew control (0.06 ns/ step) rw 01_111 2.8.4:0 rx_clk pad skew rgmii rx_clk output pad skew control (0.06 ns/ step) rw 0_1111 table 4-6: mmd register d escriptions (continued) address name description mode note 4-1 default
KSZ9031RNX ds00002117c-page 48 ? 2016 microchip technology inc. mmd address 2h, register 10h ? wake-on-lan ? control 2.10.15:14 pme output select these two bits work in conjunction with mmd address 2h, reg. 2h, bits [8] and [10] for pme_n1 and pme_n2 enable , to define the output for pins 17 and 38, respectively. led1/pme_n1 (pin 17) 00 = pme_n1 output only 01 = led1 output only 10 = led1 and pme_n1 output 11 = reserved int_n/pme_n2 (pin 38) 00 = pme_n2 output only 01 = int_n output only 10 = int_n and pme_n2 output 11 = reserved rw 00 2.10.13:7 reserved reserved rw 00_0000_0 2.10.6 magic packet detect enable 1 = enable magic-packet detection 0 = disable magic-packet detection rw 0 2.10.5 custom - packet type 3 detect enable 1 = enable custom-packet, type 3 detection 0 = disable custom-packet, type 3 detection rw 0 2.10.4 custom- packet type 2 detect enable 1 = enable custom-packet, type 2 detection 0 = disable custom - packet, type 2 detection rw 0 2.10.3 custom - packet type 1 detect enable 1 = enable custom-packet, type 1 detection 0 = disable custom - packet, type 1 detection rw 0 2.10.2 custom - packet type 0 detect enable 1 = enable custom - packet, type 0 detection 0 = disable custom - packet, type 0 detection rw 0 2.10.1 link-down detect enable 1 = enable link-down detection 0 = disable link-down detection rw 0 2.10.0 link-up detect enable 1 = enable link-up detection 0 = disable link-up detection rw 0 mmd address 2h, register 11h ? w ake-on-lan ? magic packet, mac-da-0 2.11.15:0 magic packet mac-da-0 this register stores the lower two bytes of the destination mac address for the magic packet . bit [15:8] = byte 2 (mac address [15:8]) bit [7:0] = byte 1 (mac address [7:0]) the upper four bytes of the destination mac address are stored in the following two registers. rw 0000_0000_0000_00 00 table 4-6: mmd register d escriptions (continued) address name description mode note 4-1 default
? 2016 microchip technology inc. ds00002117c-page 49 KSZ9031RNX mmd address 2h, register 12h ? wake-on-lan ? magic packet, mac-da-1 2.12.15:0 magic packet mac-da-1 this register stores the middle two bytes of the destination mac address for the magic packet . bit [15:8] = byte 4 (mac address [31:24]) bit [7:0] = byte 3 (mac address [23:16]) the lower two bytes and upper two bytes of the destination mac address are stored in the previous and following registers, respectively. rw 0000_0000_0000_00 00 mmd address 2h, register 13h ? wake-on-lan ? magic packet, mac-da-2 2.13.15:0 magic packet mac-da-2 this register stores the upper two bytes of the destination mac address for the magic packet . bit [15:8] = byte 6 (mac address [47:40]) bit [7:0] = byte 5 (mac address [39:32]) the lower four bytes of the destination mac address are stored in the previous two registers. rw 0000_0000_0000_00 00 mmd address 2h, register 14h ? wake-on-lan ? customized packet, type 0, expected crc 0 mmd address 2h, register 16h ? wake-on-lan ? customized packet, type 1, expected crc 0 mmd address 2h, register 18h ? wake-on-lan ? customized packet, type 2, expected crc 0 mmd address 2h, register 1ah ? wake-on-lan ? customized packet, type 3, expected crc 0 2.14.15:0 2.16.15:0 2.18.15:0 2.1a.15:0 custom packet type x crc 0 this register stores the upper two bytes for the expected crc . bit [15:8] = byte 2 (crc [15:8]) bit [7:0] = byte 1 (crc [7:0]) the lower two bytes for the expected crc are stored in the following register. rw 0000_0000_0000_00 00 mmd address 2h, register 15h ? wake-on-lan ? customized packet, type 0, expected crc 1 mmd address 2h, register 17h ? wake-on-lan ? customized packet, type 1, expected crc 1 mmd address 2h, register 19h ? wake-on-lan ? customized packet, type 2, expected crc 1 mmd address 2h, register 1bh ? wake-on-lan ? customized packet, type 3, expected crc 1 2.15.15:0 2.17.15:0 2.19.15:0 2.1b.15:0 custom packet type x crc 1 this register stores the lower two bytes for the expected crc . bit [15:8] = byte 4 (crc [31:24]) bit [7:0] = byte 3 (crc [23:16]) the upper two bytes for the expected crc are stored in the previous register. rw 0000_0000_0000_00 00 mmd address 2h, register 1ch ? wake-on-lan ? customized packet, type 0, mask 0 mmd address 2h, register 20h ? wake-on-lan ? customized packet, type 1, mask 0 mmd address 2h, register 24h ? wake-on-lan ? customized packet, type 2, mask 0 mmd address 2h, register 28h ? wake-on-lan ? customized packet, type 3, mask 0 2.1c.15:0 2.20.15:0 2.24.15:0 2.28.15:0 custom packet type x mask 0 this register selects the bytes in the first 16 bytes of the packet (bytes 1 through 16) that will be used for crc calculation. for each bit in this register, 1 = byte is selected for crc calculation 0 = byte is not selected for crc calculation the register-bit to packet-byte mapping is as fol- lows: bit [15]: byte 16 ?? bit [2]: byte 2 bit [0]: byte 1 rw 0000_0000_0000_00 00 table 4-6: mmd register d escriptions (continued) address name description mode note 4-1 default
KSZ9031RNX ds00002117c-page 50 ? 2016 microchip technology inc. mmd address 2h, register 1dh ? wake-on-lan ? customized packet, type 0, mask 1 mmd address 2h, register 21h ? wake-on-l an ? customized packet, type 1, mask 1 mmd address 2h, register 25h ? wake-on-l an ? customized packet, type 2, mask 1 mmd address 2h, register 29h ? wake-on-l an ? customized packet, type 3, mask 1 2.1d.15:0 2.21.15:0 2.25.15:0 2.29.15:0 custom packet type x mask 1 this register selects the bytes in the second 16 bytes of the packet (bytes 17 thru 32) that will be used for crc calculation. for each bit in this register, 1 = byte is selected for crc calculation 0 = byte is not selected for crc calculation the register-bit to packet-byte mapping is as fol- lows: bit [15]: byte 32 ?? bit [2]: byte 18 bit [0]: byte 17 rw 0000_0000_0000_00 00 mmd address 2h, register 1eh ? wake-on-lan ? customized packet, type 0, mask 2 mmd address 2h, register 22h ? wake-on-l an ? customized packet, type 1, mask 2 mmd address 2h, register 26h ? wake-on-l an ? customized packet, type 2, mask 2 mmd address 2h, register 2ah ? wake-on-lan ? customized packet, type 3, mask 2 2.1e.15:0 2.22.15:0 2.26.15:0 2.2a.15:0 custom packet type x mask 2 this register selects the bytes in the third 16 bytes of the packet (bytes 33 through 48) that will be used for crc calculation. for each bit in this register, 1 = byte is selected for crc calculation 0 = byte is not selected for crc calculation the register-bit to packet-byte mapping is as fol- lows: bit [15]: byte 48 ?? bit [2]: byte 34 bit [0]: byte 33 rw 0000_0000_0000_00 00 mmd address 2h, register 1fh ? wake-on-lan ? customized packet, type 0, mask 3 mmd address 2h, register 23h ? wake-on-l an ? customized packet, type 1, mask 3 mmd address 2h, register 27h ? wake-on-l an ? customized packet, type 2, mask 3 mmd address 2h, register 2bh ? wake-on-lan ? customized packet, type 3, mask 3 2.1f.15:0 2.23.15:0 2.27.15:0 2.2b.15:0 custom packet type x mask 3 this register selects the bytes in the fourth 16 bytes of the packet (bytes 49 through 64) that will be used for crc calculation. for each bit in this register, 1 = byte is selected for crc calculation 0 = byte is not selected for crc calculation the register-bit to packet-byte mapping is as fol- lows: bit [15]: byte 64 ?? bit [2]: byte 50 bit [0]: byte 49 rw 0000_0000_0000_00 00 mmd address 1ch, register 4h ? analog control 4 1c.4.15:11 reserved reserved rw 0000_0 1c.4.10 10base-te mode 1 = 10base-te (1.75v tx amplitude) 0 = standard 10base-t (2.5v tx amplitude) rw 0 1c.4.9:0 reserved reserved rw 00_1111_1111 table 4-6: mmd register d escriptions (continued) address name description mode note 4-1 default
? 2016 microchip technology inc. ds00002117c-page 51 KSZ9031RNX note 4-1 rw = read/write; ro = read only; wo = write only; lh = latch high. mmd address 1ch, register 23h ? edpd control 1c.23.15:1 reserved reserved rw 0000_0000_0000_00 0 1c.23.0 edpd mode enable energy-detect power-down mode 1 = enable 0 = disable rw 0 table 4-6: mmd register d escriptions (continued) address name description mode note 4-1 default
KSZ9031RNX ds00002117c-page 52 ? 2016 microchip technology inc. 5.0 operational characteristics 5.1 absolute maximum ratings* supply voltage (v in ) (dvddl, avddl, avddl_pll)...................................................................................................... .......... ?0.5v to +1.8v (avddh)........................................................................................................................ ............................ ?0.5v to +5.0v (dvddh) ............. ............... .............. .............. .............. .............. .............. ........... ........... ........................... ?0.5v to +5.0v input voltage (all inputs)..................................................................................................... ....................... ?0.5v to +5.0v output voltage (all outputs)................................................................................................... .................... ?0.5v to +5.0v lead temperature (soldering, 10s) .............................................................................................. ......................... +260c storage temperature (t s ) ................ .............. .............. .............. .............. .............. .............. .............. .... ?55c to +150c *exceeding the absolute maximum rating may damage the dev ice. stresses greater than the absolute maximum rating may cause permanent damage to the device. operation of the device at these or any other conditions above those spec- ified in the operating sections of this specification is not implied. maximum conditions for extended periods may affect reliability. 5.2 operating ratings** supply voltage (dvddl, avddl, avddl_pll)...................................................................................................... .. +1.140v to +1.260v (avddh @ 3.3v)................................................................................................................. .............. +3.135v to +3.465v (avddh @ 2.5v; commercial temp. only)........................................................................................ +2 .375v to +2.625v (dvddh @ 3.3v) ......... .............. .............. .............. .............. .............. ........... ........... ............ ............. +3.135v to +3.465v (dvddh @ 2.5v) ......... .............. .............. .............. .............. .............. ........... ........... ............ ............. +2.375v to +2.625v (dvddh @ 1.8v) ......... .............. .............. .............. .............. .............. ........... ........... ............ ............. +1.710v to +1.890v ambient temperature (t a commercial: KSZ9031RNXc)...................................................................................................... ..........0c to +70c (t a industrial: KSZ9031RNXi)............ .............. .............. .............. .............. ............ ........... ........... ............ ?40c to +85c (t a automotive: KSZ9031RNXu)............. ......................................................................................... ....... ?40c to +85c (t a automotive: KSZ9031RNXv) .. .................................................................................................... ..... ?40c to +105c maximum junction temperature (t j max.) ........................................................................................................... +125c thermal resistance ( ja )............................................................................................................................. + 36.34c/w thermal resistance ( jc ).............................................................................................................................. . +9.47c/w **the device is not guaranteed to function outside its operating ratings. note: do not drive input signals without power supplied to the device.
? 2016 microchip technology inc. ds00002117c-page 53 KSZ9031RNX 6.0 electrical characteristics t a = 25c. specification is for packaged product only. table 6-1: supply current - core/digital i/o parameters symbol min. typ. max. units note 1.2v total of: dvddl (digital core) + avddl (analog core) + avddl_pll (pll) i core ?210? ma 1000base-t link-up (no traffic) ?221? 1000base-t full-duplex @ 100% utilization ? 63.6 ? 100base-tx li nk-up (no traffic) ?63.8? 100base-tx full-duplex @ 100% utilization ? 7.1 ? 10base-t link-up (no traffic) ?7.7? 10base-t full-duplex @ 100% utilization ?1.0? software power-down mode (reg. 0.11 = 1) ?0.7? chip power-down mode (strap-in pins mode[3:0] = 0111) 1.8v for digital i/o (rgmii operating @ 1.8v) i dvddh_1.8 ?11.2? ma 1000base-t link-up (no traffic) ?23.6? 1000base-t full-duplex @ 100% utilization ? 8.4 ? 100base-tx link-up (no traffic) ?9.8? 100base-tx full-duplex @ 100% utilization ? 3.6 ? 10base-t link-up (no traffic) ?5.6? 10base-t full-duplex @ 100% utilization ?5.5? software power-down mode (reg. 0.11 = 1) ?0.3? chip power-down mode (strap-in pins mode[3:0] = 0111) 2.5v for digital i/o (rgmii operating @ 2.5v) i dvddh_2.5 ?14.7? ma 1000base-t link-up (no traffic) ?31.5? 1000base-t full-duplex @ 100% utilization ? 10.5 ? 100base-tx li nk-up (no traffic) ?13.0? 100base-tx full-duplex @ 100% utilization ? 6.3 ? 10base-t link-up (no traffic) ?9.0? 10base-t full-duplex @ 100% utilization ?6.7? software power-down mode (reg. 0.11 = 1) ?0.7? chip power-down mode (strap-in pins mode[3:0] = 0111)
KSZ9031RNX ds00002117c-page 54 ? 2016 microchip technology inc. note 6-1 equivalent to current draw through external transf ormer center taps for ph y transceivers with current- mode transmit drivers. 3.3v for digital i/o (rgmii operating @ 3.3v) i dvddh_3.3 ?19.5? ma 1000base-t link-up (no traffic) ?41.5? 1000base-t full-duplex @ 100% utilization ? 13.9 ? 100base-tx link-up (no traffic) ?17.2? 100base-tx full-duplex @ 100% utilization ? 11.5 ? 10base-t link-up (no traffic) ?13.7? 10base-t full-duplex @ 100% utilization ?9.3? software power-down mode (reg. 0.11 = 1) ?2.2? chip power-down mode (strap-in pins mode[3:0] = 0111) table 6-2: supply current - transceiver ( note 6-1 ) parameters symbol min. typ. max. units note 2.5v for transceiver (recommended for commercial temperature range operation only) i avddh_2.5 ?58.8? ma 1000base-t link-up (no traffic) ?57.9? 1000base-t full-duplex @ 100% utilization ? 24.9 ? 100base-tx link-up (no traffic) ?24.9? 100base-tx full-duplex @ 100% utilization ? 11.5 ? 10base-t link-up (no traffic) ?25.3? 10base-t full-duplex @ 100% utilization ?3.1? software power-down mode (reg. 0.11 = 1) ?0.02? chip power-down mode (strap-in pins mode[3:0] = 0111) 3.3v for transceiver parameter i avddh_3.3 ?67.4? ma 1000base-t link-up (no traffic) ?66.3? 1000base-t full-duplex @ 100% utilization ? 28.7 ? 100base-tx link-up (no traffic) ?28.6? 100base-tx full-duplex @ 100% utilization ? 15.9 ? 10base-t link-up (no traffic) ?28.6? 10base-t full-duplex @ 100% utilization ?4.2? software power-down mode (reg. 0.11 = 1) ?0.02? chip power-down mode (strap-in pins mode[3:0] = 0111) table 6-1: supply current - core/digital i/o (continued) parameters symbol min. typ. max. units note
? 2016 microchip technology inc. ds00002117c-page 55 KSZ9031RNX table 6-3: cmos inputs parameters symbol min. typ. max. units note input high voltage v ih 2.0 ? ? v dvddh (digital i/o) = 3.3v 1.5 ? ? dvddh (digital i/o) = 2.5v 1.1 ? ? dvddh (digital i/o) = 1.8v input low voltage v il ??1.3 v dvddh (digital i/o) = 3.3v ? ? 1.0 dvddh (digital i/o) = 2.5v ? ? 0.7 dvddh (digital i/o) = 1.8v input high leakage current i ihl ?2.0 ? 2.0 a dvddh = 3.3v and v ih = 3.3v all digital input pins input low leakage current i ill ?2.0 ? 2.0 a dvddh = 3.3v and v il = 0.0v all digital input pins, except mdc, mdio, reset_n. ?120 ? ?40 dvddh = 3.3v and v il = 0.0v mdc, mdio, reset_n pins with internal pull-ups table 6-4: cmos outputs parameter symbol min. typ. max. units note output high voltage v oh 2.7 ? ? v dvddh (digital i/o) = 3.3v , i oh (min) = 10 ma all digital output pins 2.0 ? ? dvddh (digital i/o) = 2.5v, i oh (min) = 10 ma all digital output pins 1.5 ? ? dvddh (digital i/o) = 1.8v, i oh (min) = 13 ma all digital output pins, except led1, led2 output low voltage v ol ??0.3 v dvddh (digital i/o) = 3.3v , i ol (min) = 10 ma all digital output pins ??0.3 dvddh (digital i/o) = 2.5v, i ol (min) = 10 ma all digital output pins ??0.3 dvddh (digital i/o) = 1.8v, i ol (min) = 13 ma all digital output pins, except led1, led2 output tri-state leakage |i oz |??10a ? table 6-5: led outputs parameters symbol min. typ. max. units note output drive current i led 10 ? ? ma dvddh (digital i/o) = 3.3v or 2.5v, and v ol at 0.3v each led pin (led1, led2)
KSZ9031RNX ds00002117c-page 56 ? 2016 microchip technology inc. note 6-2 measured with pin input voltage level at one-half dvddh. note 6-3 measured differentially after 1:1 transformer. note 6-4 measured differentially after 1:1 transformer. table 6-6: pull-up pins ( note 6-2 ) parameters symbol min. typ. max. units note internal pull-up resistance (mdc, mdio, reset_n pins) pu 13 22 31 k ? dvddh (digital i/o) = 3.3v 16 28 39 dvddh (digital i/o) = 2.5v 26 44 62 dvddh (digital i/o) = 1.8v table 6-7: 100base-tx transmit ( note 6-3 ) parameters symbol min. typ. max. units note peak differential output voltage v o 0.95 ? 1.05 v 100 ? termination across differential output output voltage imbalance v imb ?? 2 %100 ? termination across differential output rise/fall time t r , t f 3?5ns ? rise/fall time imbalance ? 0 ? 0.5 ns ? duty cycle distortion ? ? ? 0.25 ns ? overshoot ? ? ? 5 % ? output jitter ? ? 0.7 ? ns peak-to-peak table 6-8: 10base-t transmit ( note 6-4 ) parameters symbol min. typ. max. units note peak differential output voltage v p 2.2 ? 2.8 v 100 ? termination across differential output jitter added ? ? ? 3.5 ns peak-to-peak harmonic rejection ? ? ?31 ? db transmit all-one signal sequence table 6-9: 10base-t receive parameters symbol min. typ. max. units note squelch threshold v sq 300 400 ? mv 5 mhz square wave table 6-10: transmitter - drive setting parameters symbol min. typ. max. units note reference voltage of i set v set ?1.2? v r(i set ) = 12.1 k ? table 6-11: ldo controller - drive range parameters symbol min. typ. max. units note output drive range for ldo_o (pin 43) to gate input of p - channel mosfet v ldo_o 0.85 ? 2.8 v avddh = 3.3v for mosfet source voltage 0.85 ? 2.0 avddh = 2.5v for mosfet source voltage (recommended for commer- cial temperature range operation only)
? 2016 microchip technology inc. ds00002117c-page 57 KSZ9031RNX 7.0 timing diagrams 7.1 rgmii timing as the default, after power-up or reset, the KSZ9031RNX rg mii timing conforms to the timing requirements in the rgmii version 2.0 specification for internal phy chip delay. for the transmit path (mac to KSZ9031RNX), the KSZ9031RNX does not add any delay locally at its gtx_clk, tx_en and txd[3:0] input pins, and expects the gtx_clk delay to be provided on-chip by the mac. if mac does not provide any delay or insufficient delay for the gtx_clk, the KSZ9031RNX has pad skew registers that can provide up to 1.38 ns on-chip delay. for the receive path (KSZ9031RNX to mac), the KSZ9031RNX adds 1.2 ns typical delay to the rx_clk output pin with respect to rx_dv and rxd[3:0] output pins. if necessa ry, the KSZ9031RNX has pad skew registers that can adjust the rx_clk on-chip delay up to 2.58 ns from the 1.2 ns default delay. it is common to implement rgmii phy-to-mac designs that ei ther phy, mac, or both phy and mac are not fully rgmii v2.0 compliant with on-chip clock delay. these combinatio ns of mixed rgmii v1.3/v2.0 designs and plus sometimes non-matching rgmii pcb trace routings require a review of the entire rgmii system timings (phy on-chip, pcb trace delay, mac on-chip) to compute the aggregate clock delay and determine if the clock delay timing is met. if timing adjust- ment is needed, pad skew registers ar e provided by the KSZ9031RNX. refer to rgmii pad skew registers section. the following figure 7-1 , figure 7-2 , and table 7-1 from the rgmii v2.0 specification are provided as references to understanding rgmii v1.3 external delay and rgmii v2.0 on-chip delay timings. figure 7-1: rgmii v2.0 spec (multiplexing and timing diagram ? original rgmii (v1.3) with external delay)
KSZ9031RNX ds00002117c-page 58 ? 2016 microchip technology inc. figure 7-2: rgmii v2.0 spec (multiplexing and timing diagram ? rgmii-id (v2.0) with internal chip delay) the following notes prov ide clarification for figure 7-2 . txc (source data) , solid line, is the mac gtx_clk clock output ti ming per rgmii v1.3 specification (pcb delay line required or phy internal delay required) txc (source data) with internal delay added , dotted line, is the mac gtx_ clk clock output timing per rgmii v2.0 specification (no pcb delay r equired and no phy internal delay required) rxc (source data) , solid line, is the phy rx_clk clock output timi ng per rgmii v1.3 specification (pcb delay line required or mac internal delay required) rxc (source data) with internal delay added , dotted line, is the phy rx_clk clock output timing per rgmii v2.0 specification (no pcb delay r equired and no mac internal delay required) table 7-1: rgmii v2.0 specification parameter description min. typ. max. units t skew t data-to-clock output skew (at transmitter) per rgmii v1.3 (external delay) ?500 ? 500 ps t skew r data-to-clock input skew (at receiver) per rgmii v1.3 (external delay) 1.0 ? 2.6 ns t setup t data-to-clock output setup (at transmitter ? inte- grated delay) 1.2 2.0 ? t hold t clock-to-data output hold (at transmitter ? inte- grated delay) 1.2 2.0 ? t setup r data-to-clock input setup (at receiver ? integrated delay) 1.0 2.0 ? t hold r clock-to-data input hold (at receiver ? integrated delay) 1.0 2.0 ? t cyc (1000base-t) clock cycle dur ation for 1000base-t 7.2 8.0 8.8 t cyc (100base-tx) clock cycle dur ation for 100base-tx 36 40 44 t cyc (10base-t) clock cycle durat ion for 10base-t 360 400 440 txc(source data) txc with internal delay added txd[8:5][3:0] txd[7:4][3:0] tx_ctl txc (at receiver) rxc (source data) rxd[8:5][3:0] rxd[7:4][3:0] rx_ctl rxc (at receiver) txd[3:0] txd[8:5] txd[7:4] t setup t t hold t t setup r t hold r txd[4] txen txd[9] txerr rxc with internal delay added rxd[3:0] rxd[8:5] rxd[7:4] t setup t t hold t t setup r t hold r rxd[4] rxdv rxd[9] rxerr
? 2016 microchip technology inc. ds00002117c-page 59 KSZ9031RNX the rgmii version 2.0 specification defi nes the rgmii data-to-clock skews only for 1000 mbps operation, which uses both clock edges for sampling the data and control signals at the 125 mhz clock frequency (8 ns period). for 10/100 mbps operations, the data signals are sampled on the rising clock edge and the control signals are sampled on both clock edges. with slower clock frequencies, 2.5 mhz (400 ns period) for 10 mbps and 25 mhz (40 ns period) for 100 mbps, the rgmii data-to-clock skews for 10/100 mbps operations will have greater timing margins than for 1000 mbps operation, and therefore can be relaxed from 2.6 ns (maximum) for 1000 mbps to 160 ns (maximum) for 10 mbps and 16 ns (maximum) for 100 mbps.
KSZ9031RNX ds00002117c-page 60 ? 2016 microchip technology inc. figure 7-3: auto-negotiation fast link pulse (flp) timing the KSZ9031RNX fast link pulse (flp) burst-to-burst transm it timing for auto-negotiation defaults to 8 ms. ieee 802.3 standard specifies this timing to be 16 ms 8 ms . some phy link partners need to receive the flp with 16 ms centered timing; otherwise, there can be intermi ttent link failures and long link-up times. after KSZ9031RNX power-up/reset, program the following r egister sequence to set the flp timing to 16 ms: 1. write register dh = 0x0000 // set up register address for mmd ? device address 0h 2. write register eh = 0x0004 // select register 4h of mmd ? device address 0h 3. write register dh = 0x4000 // select register data for mmd ? device address 0h, register 4h 4. write register eh = 0x0006 // write value 0x 0006 to mmd ? device address 0h, register 4h 5. write register dh = 0x0000 // set up register address for mmd ? device address 0h 6. write register eh = 0x0003 // select register 3h of mmd ? device address 0h 7. write register dh = 0x4000 // select register data for mmd ? device address 0h, register 3h 8. write register eh = 0x1a80 // write value 0x 1a80 to mmd ? device address 0h, register 3h 9. write register 0h, bit [9] = 1 // restart auto-negotiation the above setting for 16 ms flp transmit timing is compatible with all phy link partners. table 7-2: auto-negotiation fast li nk pulse (flp) timing parameters timing parameter description min. typ. max. units t btb flp burst to flp burst 8 16 24 ms t flpw flp burst width ? 2 ? t pw clock/data pulse width ? 100 ? ns t ctd clock pulse to data pulse 55.5 64 69.5 s t ctc clock pulse to clock pulse 111 128 139 ? number of clock/data pulses per flp burst 17 ? 33 ?
? 2016 microchip technology inc. ds00002117c-page 61 KSZ9031RNX figure 7-4: mdc/mdio timing the typical mdc clock frequency is 2.5 mhz (400 ns clock period). the KSZ9031RNX can operate with mdc clock frequencies gen erated from bit banging with gpio pin in the 10s/100s of hertz and have been tested up to a mdc clock frequency of 8.33 mhz (120 ns clock period). test condition for 8.33 mhz is for one KSZ9031RNX phy on the mdio line with a 1.0 k ? pull-up to the dvddh supply rail. table 7-3: mdc/mdio timing parameters timing parameter description min. typ. max. units t p mdc period 120 400 ? ns t md1 mdio (phy input) setup to rising edge of mdc 10 ? ? t md2 mdio (phy input) hold from rising edge of mdc 10 ? ? t md3 mdio (phy output) delay from rising edge of mdc 0 ? ?
KSZ9031RNX ds00002117c-page 62 ? 2016 microchip technology inc. figure 7-5: power-up/p ower-down/reset timing note 1: the recommended power-up sequence is to have the transceiver (avddh) and digital i/o (dvddh) voltages power up before the 1.2v core (dvddl, avddl, avddl_pll) vo ltage. if the 1.2v core must power up first, the maxi- mum lead time for the 1.2v core voltage with respect to the transceiver and digital i/o voltages should be 200 s. there is no power sequence requirement between transceiver (avddh) and digital i/o (dvddh) power rails. the power-up waveforms should be monotonic for all supply voltages to the KSZ9031RNX. note 2: after the de-assertion of reset, wait a minimum of 100 s before starting programming on the miim (mdc/mdio) interface. note 3: the recommended power-down sequence is to have th e 1.2v core voltage power-down before powering down the transceiver and digital i/o voltages. before the next power-up cycle, all supply voltages to t he KSZ9031RNX should reach less than 0.4v and there should be a minimum wait time of 150 ms from power-off to power-on. table 7-4: power-up/power-down/reset timing parameters timing parameter description min. typ. max. units t vr supply voltages rise time (must be monotonic) 200 ? ? s t sr stable supply voltages to de-assertion of reset 10 ? ? ms t cs strap-in pin configuration setup time 5 ? ? ns t ch strap-in pin configuration hold time 5 ? ? t rc de-assertion of reset to strap-in pin output 6 ? ? t pc supply voltages cycle off-to-on time 150 ? ? ms t sr t cs t ch t rc supply voltages reset_n strap-in value strap-in / output pin core (dvddl, avddl, avddl_pll) transceiver (avddh), digital i/os (dvddh) t vr t pc note 1 note 2 note 3
? 2016 microchip technology inc. ds00002117c-page 63 KSZ9031RNX 8.0 reset circuit the following are some reset circuit suggestions. figure 8-1 illustrates the reset circuit for powering up the KSZ9031RNX if reset is triggered by the power supply. figure 8-1: reset circuit if triggered by the power supply figure 8-2 illustrates the reset circuit for applications where reset is driven by another device (for example, the cpu or an fpga). at power-on-reset, r, c, and d1 provide the monotonic rise time to reset the KSZ9031RNX device. the rst_out_n from the cpu/fpga provid es the warm reset after power-up. the KSZ9031RNX and cpu/fpga references the same digital i/o voltage (dvddh). figure 8-2: recommended reset circuit for cpu/fpga reset output figure 8-3 illustrates the reset circuit with an mic826 voltage supervisor driving the KSZ9031RNX reset input. dvddh d1: 1n4148 d1 r 10k KSZ9031RNX reset_n c 10f dvddh KSZ9031RNX d1 r 10k reset_n c 10f d2 cpu/fpga rst_out_n d1, d2: 1n4148
KSZ9031RNX ds00002117c-page 64 ? 2016 microchip technology inc. figure 8-3: reset circuit with mic826 voltage supervisor KSZ9031RNX mic826 part number reset# reset threshold dvddh = 3.3v, 2.5v, or 1.8v reset_n dvddh dvddh mic826tymt / 3.075v mic826zymt / 2.315v mic826wymt / 1.665v
? 2016 microchip technology inc. ds00002117c-page 65 KSZ9031RNX 9.0 reference circuits ? led strap-in pins the pull-up and pull-down reference circuits for the led2 /phyad1 and led1/phyad0 strapping pins are shown in figure 9-1 for 3.3v and 2.5v dvddh. figure 9-1: reference circuits for led strapping pins for 1.8v dvddh, led indication support requires voltage le vel shifters between led[2:1] pins and led indicator diodes to ensure the multiplexed phyad[ 1:0] strapping pins are latched in high /low correctly. if led indicator diodes are not implemented, the phyad[1:0] strapping pins just need 10 k ? pull-up to 1.8v dvddh for a value of 1, and 1.0 k ? pull-down to ground for a value of 0. led pin 220 10k pull-up ksz9031r nx 220 pull-down ksz9031r nx led pin dvddh = 3.3v, 2.5v dvddh = 3.3v, 2.5v 1k
KSZ9031RNX ds00002117c-page 66 ? 2016 microchip technology inc. 10.0 reference clock - connection and selection a crystal or external clock source, such as an oscillator, is used to provide the reference clock for the KSZ9031RNX. the reference clock is 25 mhz for all operating modes of the KSZ9031RNX. the KSZ9031RNX uses the avddh supply, analog 3.3v (or an alog 2.5v option for commercial temperature only), for the crystal/clock pins (xi, xo). if the 25 mhz reference clo ck is provided externally, the xi input pin should have a min- imum clock voltage peak-to-peak (v pp ) swing of 2.5v reference to ground. if v pp is less than 2.5v, series capacitive coupling is recommended. with capacitive coupling, the v pp swing can be down to 1.5v. maximum v pp swing is 3.3v +5%. figure 10-1 and table 10-1 show the reference clock connection to xi and xo of the KSZ9031RNX, and the reference clock selection criteria. figure 10-1: 25 mhz crystal/oscillator reference clock connection 11.0 on-chip ldo controlle r - mosfet selection if the optional ldo controller is used to generate 1.2v for the core voltage, the selected mosfet should exceed the following minimum requirements: ? p-channel ? 500 ma (continuous current) ? 3.3v or 2.5v (source ? input voltage) ? 1.2v (drain ? output voltage) ?v gs in the range of: - (?1.2v to ?1.5v) @ 500 ma for 3.3v source voltage - (?1.0v to ?1.1v) @ 500 ma for 2.5v source voltage the v gs for the mosfet needs to be operat ing in the constant current saturated region, and not towards the v gs(th) , the threshold voltage for the cut-off region of the mosfet. see table 6-11 for ldo controller output driving ra nge to the gate input of the mosfet. refer to application note anlan206 ? ksz9031 gigabit ph y optimized power scheme for high efficiency, low-power consumption and dissipation as a design reference. table 10-1: 25 mhz crystal/refer ence clock selec tion criteria characteristics value frequency 25 mhz frequency tolerance (max.) 50 ppm crystal series resistance (typ.) 40 ? total period jitter (peak-to-peak) <100 ps 22pf 22pf nc xi xo xi xo 25 mhz xtal 50ppm 25 mhz osc 50ppm
? 2016 microchip technology inc. ds00002117c-page 67 KSZ9031RNX 12.0 magnetic - connec tion and selection a 1:1 isolation transformer is required at the line interfac e. use one with integrated common-mode chokes for designs exceeding fcc requirements. an optional auto-transformer stage following the chokes provides additional common- mode noise and signal attenuation. the KSZ9031RNX design incorporates voltage-mod e transmit drivers and on-chip terminations. with the voltage-mode implementation, the transmit drivers supply the common-mode voltages to the four differential pairs. therefore, the four transforme r center tap pins on the KSZ9031RNX side should not be connected to any power supply source on the board; rather, th e center tap pins should be separated from one another and connected through separate 0.1 f common-mode capacitors to ground. separation is required because the common-mode voltage could be different between the four differential pa irs, depending on the connected speed mode. figure 12-1 shows the typical gigabit magnetic interface circuit for the KSZ9031RNX. figure 12-1: typical gigabit magnetic interface circuit table 12-1 lists recommended magnetic characteristics. table 12-2 is a list of compatible single-port magnetics with separated transformer center tap pins on the g-phy chip side that can be used with the KSZ9031RNX. table 12-1: magnetics selection criteria parameter value test conditions turns ratio 1 ct : 1 ct ? open-circuit inductance (min.) 350 h 100 mv, 100 khz, 8 ma insertion loss (max.) 1.0 db 0 mhz to 100 mhz hipot (min.) 1500 v rms ? table 12-2: compatibl e single-port 10/100/1000 magnetics manufacturer part number auto-transformer temperature range magnetic + rj-45 bel fuse 0826-1g1t-23-f yes 0c to 70c yes halo tg1g-e001nzrl no ?40c to 85c no 1 2 3 7 8 4 5 6 4x75 1000 pf / 2kv r j - 45 connector chassis ground (4 x 0.1f) txrxp_a txrxm_a ksz 9031r nx signal ground txrxp_b txrxm_b txrxp_c txrxm_c txrxp_d txrxm_d
KSZ9031RNX ds00002117c-page 68 ? 2016 microchip technology inc. halo tg1g-s001nzrl no 0c to 70c no halo tg1g-s002nzrl yes 0c to 70c no pulse h5007nl yes 0c to 70c no pulse h5062nl yes 0c to 70c no pulse hx5008nl yes ?40c to 85c no pulse jk0654219nl yes 0c to 70c yes pulse jk0-0136nl no 0c to 70c yes tdk tla-7t101lf no 0c to 70c no wurth/midcom 000-7093-37r-lf1 yes 0c to 70c no table 12-2: compatible single-por t 10/100/1000 magnetics (continued) manufacturer part number auto-transformer temperature range magnetic + rj-45
? 2016 microchip technology inc. ds00002117c-page 69 KSZ9031RNX 13.0 package outlines note: for the most current package drawings, please se e the microchip packaging specification located at http://www.microchip.com/packaging figure 13-1: 48-lead qfn 7 mm x 7 mm pa ckage with 3.5 mm x 3.5 mm exposed pad area
KSZ9031RNX ds00002117c-page 70 ? 2016 microchip technology inc. figure 13-2: 48-lead qfn 7 mm x 7 mm pa ckage with 5.1 mm x 5.1 mm exposed pad area title 48 lead qfn 7x7mm package outline & recommended land pattern drawing # qfn77-48ld-pl-1 unit mm note: 1. max package warpage is 0.05mm. 2. max allowable burr is 0.076mm in all directions. 3. pin #1 is on top will be laser marked. 4. red circle in land pattern indicates thermal via. size should be 0.30-0.35mm in diameter and should be connected to gnd for max thermal performance. pitch is 1.00mm. 5. green rectangles (shaded area) represent solder stencil opening on exposed pad area. recommended size is 1.00x1.00mm, spacing is 0.25mm. note: 1, 2, 3 0.250.05 5.50 ref. 0.50 bsc 0.400.05 pin #1 id chamfer 0.35x45 48 1 2 7.000.05 7.000.05 top view note: 1, 2, 3 bottom view 0.850.05 0.253 (ref) 0.00-0.05 note: 1, 2, 3 side view 5.100.05 exp.dap 5.100.05 exp.dap
? 2016 microchip technology inc. ds00002117c-page 71 KSZ9031RNX figure 13-3: 48-lead qfn 7 mm x 7 mm pa ckage with 5.1 mm x 5.1 mm exposed pad area recommended land pattern pod-land pattern drawing #: qfn77-48ld-pl-1-c
KSZ9031RNX ds00002117c-page 72 ? 2016 microchip technology inc. figure 13-4: 48-lead wqfn 7 mm x 7 mm package with 5.05 mm x 5.05 mm exposed pad area
? 2016 microchip technology inc. ds00002117c-page 73 KSZ9031RNX figure 13-5: 48-lead wqfn 7 mm x 7 mm package with 5.05 mm x 5.05 mm exposed pad area recommended land pattern
KSZ9031RNX ds00002117c-page 74 ? 2016 microchip technology inc. appendix a: data sheet revision history table a-1: revision history revision section/figure/entry correction ds00002117c (07-26-16) all removed energy efficient ethernet functionality. ds00002117b (05-24-16) 10.0 reference clock - connection and selection specified jitter for 25 mhz reference crystal/clock. ds00002117a (03-14-16) converted micrel data sheet KSZ9031RNX to microchip ds00002117a. minor text changes throughout. wake-on-lan ? custom- ized packet, expected crc 1 and crc 2 registers. the ?lower? and ?upper? denotations for the two bytes of expected crc are swapped in the previ- ous revision. product identification system specified exposed pad size area for packages. package information corrected information for copper wire part numbers (KSZ9031RNXcc, KSZ9031RNXic) to 48-pin (7 mm x 7 mm) qfn with (5.1 mm x 5.1 mm) exposed pad area. this is a data sheet correction. there is no change to the copper wire package.
? 2016 microchip technology inc. ds00002117c-page 75 KSZ9031RNX the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site con- tains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), te chnical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of semi- nars and events, listings of microchip sales offi ces, distributors and factory representatives customer change notification service microchip?s customer notification servic e helps keep customers current on microc hip products. subscribers will receive e-mail notification whenever there are changes, updates, revisi ons or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under ?support?, click on ?customer change notifi- cation? and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this docu- ment. technical support is available through the web site at: http://microchip.com/support
KSZ9031RNX ds00002117c-page 76 ? 2016 microchip technology inc. product identification system to order or obtain information, e.g., on pricing or de livery, refer to the factory or the listed sales office . device: ksz9031 interface: r = rgmii package: nx = 48-pin qfn or wqfn temperature: c = 0 ? c to +70 ? c (commercial) i = ?40 ? c to +85 ? c (industrial) u = ?40 ? c to +85 ? c (automotive) v = ?40 ? c to +105 ? c (automotive extended) bond wire: a = gold c = copper examples: a) KSZ9031RNXca rgmii interface 48-pin qfn (pb-free, 3.5 mm x 3.5 mm epad) commercial temperature gold wire bonding b) KSZ9031RNXcc rgmii interface 48-pin qfn (pb-free, 5.1 mm x 5.1 mm epad) commercial temperature copper wire bonding c) KSZ9031RNXia rgmii interface 48-pin qfn (pb-free, 3.5 mm x 3.5 mm epad) industrial temperature gold wire bonding d) KSZ9031RNXic rgmii interface 48-pin qfn (pb-free, 5.1 mm x 5.1 mm epad) industrial temperature copper wire bonding e) KSZ9031RNXua rgmii interface 48-pin wqfn (pb-free, 5.05 mm x 5.05 mm epad) automotive temperature gold wire bonding f) KSZ9031RNXva rgmii interface 48-pin wqfn (pb-free, 5.05 mm x 5.05 mm epad) automotive extended temperature gold wire bonding part no. x xx package interface device x temperature x bond wire
? 2016 microchip technology inc. ds00002117c-page 77 information contained in this publication regarding device applications and the like is provided on ly for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with yo ur specifications. microchip make s no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fi tness for purpose . microchip disclaims all liability arising from this information and its use. use of micro- chip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemn ify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, impl icitly or otherwise, under any microchip intellectual property rights unless otherwise stated. trademarks the microchip name and logo, the microchip l ogo, anyrate, dspic, flashflex, flexpw r, heldo, jukeblox, keeloq, keeloq logo, kleer, lancheck, link md, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. clockworks, the embedded control solutions company, ethersyn ch, hyper speed control, hyperlight load, intellimos, mtouch, precision edge, and quiet-wire are registered tradem arks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, any capacitor, anyin, anyout, body com, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dynamic average matching, dam, ecan, ethergreen, in-circuit se rial programming, icsp, inter-c hip connectivity, jitterblocker, kleernet, kleernet logo, miwi, motorbench, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem.net, pickit, pictail, puresilicon, righttouch logo, re al ice, ripple blocker, serial quad i/o, sqi, superswitcher, super switcher ii, total endurance, ts harc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of mi crochip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchi p technology incorporated in the u.s.a. silicon storage technology is a regi stered trademark of microchip tech nology inc. in other countries. gestic is a registered trademarks of microc hip technology germany ii gmbh & co. kg, a s ubsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2016, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 9781522408116 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip pr oducts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microper ipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development syst ems is iso 9001:2000 certified. quality management s ystem by dnv == iso/ts 16949 ==
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